shanyinshuiyue

shanyinshuiyue's Stars

• cxinping/PyQt5

  《PyQt5快速开发与实战》配套代码

  Language:HTML2.3k976

• jackodirks/AXI4_Master

  A VHDL implementation of an AXI4 Master

  Language:VHDL132

• cjlano/freertos

  FreeRTOS SVN clone

  Language:C219114

• Nic30/hwt

  VHDL/Verilog/SystemC code generator, simulator API written in python/c++

  Language:Python20027

• skordal/potato

  A simple RISC-V processor for use in FPGA designs.

  Language:VHDL26041

• slaclab/surf

  A huge VHDL library for FPGA development

  Language:VHDL32355

• DiegoRosales/VHDL_Modules

  VHDL Modules

  Language:C239

• aolofsson/oh

  Verilog library for ASIC and FPGA designers

  Language:Verilog1.2k284

• Xilinx/binutils

  Upstream binutils + xilinx branches

  Language:C84

• hukenovs/adc_configurator

  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

  Language:VHDL11

• kevinpt/vhdl-extras

  Flexible VHDL library

  Language:VHDL17941

• jarun/dslib

  :herb: A library of "connected" data structures

  Language:C12621

• thomasrussellmurphy/xilinx_xstug_examples

  Unzipped for ease of access: ftp://ftp.xilinx.com/pub/documentation/misc/xstug_examples.zip

  Language:VHDL41

• analogdevicesinc/hdl

  HDL libraries and projects

  Language:Verilog1.5k1.5k

• analogdevicesinc/fpgahdl_xilinx

  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC products

  Language:C87185