shanyinshuiyue

shanyinshuiyue's Stars

• SpinalHDL/SpinalHDL

  Scala based HDL

  Language:Scala1.7k331

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k512

• FFTW/fftw3

  DO NOT CHECK OUT THESE FILES FROM GITHUB UNLESS YOU KNOW WHAT YOU ARE DOING. (See below.)

  Language:C2.7k665

• EttusResearch/fpga

  The USRP™ Hardware Driver FPGA Repository

  Language:Verilog264205

• azonenberg/antikernel-ipcores

  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

  Language:SystemVerilog6013

• Hilx/Dedicated-AXI-IPs

  AXI Peripherals developed

  Language:VHDL1

• qermit/WishboneAXI

  Wishbone to AXI bridge (VHDL)

  Language:VHDL3818

• m-labs/lm32

  LatticeMico32 soft processor

  Language:Verilog10226

• fpgadeveloper/zc706-ddr3-sodimm-dma

  Example project that uses the AXI DMA peripheral to connect a custom AXI-Stream peripheral to the DDR3 SODIMM memory

  Language:C3

• Architech-Silica/Designing-a-Custom-AXI-Master-using-BFMs

  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models

  Language:VHDL3220

• tanerguven/StreamIF

  This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"

  Language:Verilog51

• k0nze/zedboard_axi4_master_burst_example

  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)

  Language:SystemVerilog378

• duskwuff/Xilinx-ISE-Makefile

  An example of how to use the Xilinx ISE toolchain from the command line

  Language:Makefile6022

• mcmenaminadrian/mb_boot

  Microblaze boot up code

  Language:Assembly1

• VHDL/awesome-vhdl

  A curated list of awesome VHDL IP cores, frameworks, libraries, software and resources.

  766

• bayandin/awesome-awesomeness

  A curated list of awesome awesomeness

  Language:Ruby32.1k3.5k

• Hilx/SysAlloc

  SysAlloc, a FPGA implemented hardware memory allocator for heterogeneous systems.

  Language:VHDL6

• cliffordwolf/PonyLink

  A single-wire bi-directional chip-to-chip interface for FPGAs

  Language:Verilog11415

• shadowsocks/shadowsocks-android

  A shadowsocks client for Android

  Language:Kotlin35.2k11.6k

• shadowsocksr-backup/shadowsocksr-android

  A ShadowsocksR client for Android

  3.5k1.3k

• Cr4sh/s6_pcie_microblaze

  PCI Express DIY hacking toolkit for Xilinx SP605. This repository is also home of Hyper-V Backdoor and Boot Backdoor, check readme for links and info

  Language:C739154

• ThirtyDegreesRay/OpenHub

  An open source GitHub Android client app, faster and concise.

  Language:Java4.2k415

• MJoergen/bcomp

  8-bit computer

  Language:VHDL81

• Koheron/koheron-sdk

  SDK for FPGA / Linux Instruments

  Language:C++10141

• cxinping/PyQt5

  《PyQt5快速开发与实战》配套代码

  Language:HTML2.3k981

• jackodirks/AXI4_Master

  A VHDL implementation of an AXI4 Master

  Language:VHDL142

• cjlano/freertos

  FreeRTOS SVN clone

  Language:C219114

• Nic30/hwt

  VHDL/Verilog/SystemC code generator, simulator API written in python/c++

  Language:Python20227

• skordal/potato

  A simple RISC-V processor for use in FPGA designs.

  Language:VHDL26341

• slaclab/surf

  A huge VHDL library for FPGA development

  Language:VHDL34655