shashankov

shashankov's Stars

• intel/fpga-partial-reconfig

  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow

  Language:SystemVerilog8727341

• andrewboutros/rad-flow

  The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.

  Language:C++27338

• Connie120/CNN

  CMU research CNN

  Language:SystemVerilog10

• vinayby/nac_v0

  Language:C++10