Verilog HDL support based on https://github.com/textmate/verilog.tmbundle TextMate package.
- Syntax highlighting for
.v
.vh
files - Simple Snippets
module
always
case
for
while
function
reg
wire
- testbench template
- etc...
- Linting
- Use
verilog.linting.linter
to select linter.- Possible values are
iverilog
xvlog
none
- Possible values are
- Icarus Verilog (
iverilog
)- Make sure the path to your Icaurus Verilog installation is present in the
PATH
variable. - If your module references other designs from other .v files, use
`include "module.v"
syntax to include them in your design. IVerilog uses these`include "path/to/file.v"
directives to refer those modules. Thepath/to/file.v
should be relative to your workspace directory. - Use
verilog.linting.iverilog.arguments
setting to add custom arguments to the linter. The argument-t null
will be added by the linter automatically - Use
verilog.linting.iverilog.runAtFileLocation
setting to run Icarus Verilog at the file location. By default, it will be run at workspace directory, requiring that`include
directives contain file paths relative to the workspace directory.
- Make sure the path to your Icaurus Verilog installation is present in the
- Xilinx Vivado Logical Simulation (
xvlog
)
- Use
- Icarus Verilog integration
- Working in:
- Windows: Yes
- Tested on Windows 10 Fall Creators Update (build 16299). Visual Studio Code 1.20.1
- Linux: Yes
- Tested on Ubuntu 14.04. Visual Studio Code 1.20.1
- macOS: Not Tested
- Windows: Yes
- Working in:
- xvlog(Vivado) integration
- Working in:
- Windows: Yes
- Ubuntu: Not Tested (Will be tested soon)
- macOS: Not Tested
- Working in:
- Please post issue if you have any new idea
mshr-h/vscode-verilog-hdl-support
Any contribution is welcome!(fixing typo, refactoring, documentation, and so on)
- Fork it ( https://github.com/mshr-h/vscode-verilog-hdl-support )
- Create your feature branch (
git checkout -b my-new-feature
) - Commit your changes (
git commit -am 'Add some feature'
) - Push to the branch (
git push origin my-new-feature
) - Create a new Pull Request
https://marketplace.visualstudio.com/items/mshr-h.VerilogHDL