Hackable FPGA based network tap based on the ZedBoard and the Quad Gigabit Ethernet FMC.
This project is designed for Vivado 2018.2. If you are using an older version of Vivado, then you MUST use an older version of this repository. Refer to the list of commits to find links to the older versions of this repository.
- Vivado 2018.2
- Ethernet FMC
- One of the above listed evaluation boards
- Zynq-7000 ZedBoard
- LPC connector (use zedboard.xdc)
This project will implement an FPGA based network tap which could be used to "listen" to the communications passing over an Ethernet cable. It is a work that is still under development.
The design in it's present state implements a pass-through between PORT0 and PORT1 of the Ethernet FMC. The pass-through is fully functional and can be tested by connecting ports 0 and 1 to separate Ethernet devices.
To use the sources in this repository, please follow these steps:
- Download the repo as a zip file and extract the files to a directory on your hard drive --OR-- Git users: clone the repo to your hard drive
- Open Windows Explorer, browse to the repo files on your hard drive.
- In the Vivado directory, you will find multiple batch files (*.bat).
Double click on the batch file that is appropriate to your hardware,
for example, double-click
build-zedboard.batif you are using the ZedBoard. This will generate a Vivado project for your hardware platform. - Run Vivado and open the project that was just created.
- Click Generate bitstream.
- When the bitstream is successfully generated, select
File->Export->Export Hardware. In the window that opens, tick "Include bitstream" and "Local to project". - Return to Windows Explorer and browse to the SDK directory in the repo.
- Double click the
build-sdk.batbatch file. The batch file will run thebuild-sdk.tclscript and build the SDK workspace containing the hardware design and the software application. - Run Xilinx SDK (DO NOT use the Launch SDK option from Vivado) and select the workspace to be the SDK directory of the repo.
- Select
Project->Build automatically. - Connect and power up the hardware.
- Open a Putty terminal to view the UART output.
- In the SDK, select
Xilinx Tools->Program FPGA. - Right-click on the application and select
Run As->Launch on Hardware (System Debugger)
The following tutorials explain the workings of the network tap:
The lwIP echo server application is used here to simplify testing the design. We run the echo server on the ZedBoard's onboard Ethernet port (connected to GEM0), which allows us to use only one PC to send and receive packets over the "tapped" link. To test this application, you must make the following connections:
- ZedBoard's on-board Ethernet connector to PORT1 of the Ethernet FMC
- PORT0 of the Ethernet FMC to your PC's Ethernet port
Now when the application is running, you will be able to send packets from your PC through PORT0, out of PORT1, into the ZedBoard's Ethernet port, from which point they will be echoed by the echo server and come back through the same path to your PC.
Check the following if the project fails to build or generate a bitstream:
Check the version specified in the Requirements section of this readme file. Note that this project is regularly maintained to the latest version of Vivado and you may have to refer to an earlier commit of this repo if you are using an older version of Vivado.
All the projects in the repo are built, synthesised and implemented to a bitstream before being committed, so if you follow the instructions, there should not be any build issues.
Vivado doesn't cope well with long directory structures, so copy/clone the repo into a short directory structure such as
C:\projects\. When working in long directory structures, you can get errors relating to missing files, particularly files
that are normally generated by Vivado (FIFOs, etc).
Feel free to modify the code for your specific application.
This project was developed by Opsero Inc., a tight-knit team of FPGA experts delivering FPGA products and design services to start-ups and tech companies. Follow our blog, FPGA Developer, for news, tutorials and updates on the awesome projects we work on.