shivampotdar

bluetooth-interfacing

Interfacing Bluetooth module HC-05 with Firebird Robot

gas-sensor-interfacing

Interface gas sensor module with the Firebird robot

openpiton

The OpenPiton Platform

quantum-computing-course

Course Material for the Quantum Computing Course by QuLabs@IIT-R

technites_strong-man

tlv_flow_lib

Generic transaction flow components (like FIFOs, arbitors, and stall pipelines) for Transaction-Level Verilog

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

shivampotdar/quantum-computing-course

Course Material for the Quantum Computing Course by QuLabs@IIT-R

shivampotdar/warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

shivampotdar/1st-CLaaS

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

shivampotdar/a2i

shivampotdar/bl_iot_sdk

shivampotdar/black-parrot

A Linux-capable host multicore for and by the world

shivampotdar/blamer-vs

📝 A VS Code extension to visually blame SVN-stored code line-by-line

shivampotdar/bsg_fpga

shivampotdar/Cache-Memory-Hog

Cache and main memory hog programs. These are programs with specific access patterns to evict the already existing cache blocks of various applications. These programs were designed to demonstrate that application performance is nearly linearly correlated with cache access rate (as shown in Section 3.1 of Subramanian et al. "The Application Slowdown Model" @ https://users.ece.cmu.edu/~omutlu/pub/application-slowdown-model_micro15.pdf)

shivampotdar/CAWS-LAB

shivampotdar/ChampSim-CAWS

shivampotdar/cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

shivampotdar/esp-2fa

shivampotdar/fossi-foundation.github.io

FOSSi Foundation Website

shivampotdar/GitHubGraduation-2021

Join the GitHub Graduation Yearbook and "walk the stage" on June 5.

shivampotdar/hypermapper

Black-box Optimizer based on Bayesian Optimization

shivampotdar/jekyll-theme-chirpy

A minimal, sidebar, responsive web design Jekyll theme, focusing on text presentation.

shivampotdar/LF-Build-a-RISC-V-Workshop

shivampotdar/linux

Linux kernel source tree

shivampotdar/notion-font-fira-code

Simple Chrome Extension to Change the Basic Font in Notion to Fira Code

shivampotdar/openpiton

The OpenPiton Platform

shivampotdar/oshcamp-2019-workshop

Materials for the OSHCamp 2019 workshop - Customising RI5CY: an open-source RISC-V core

shivampotdar/pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

shivampotdar/qorc-sdk

FreeRTOS Support for QORC

shivampotdar/RISC-V_MYTH_Workshop

Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for Me in Thirty Hours" Workshop

shivampotdar/riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

shivampotdar/riscv-perf-model

Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model

shivampotdar/shivampotdar

profile readme

shivampotdar/shivampotdar.github.io

A beautiful Jekyll theme for academics

shivampotdar/SystemDesignWorkshopCollaterals