/svANN-VLSI

The following is a scalable neural network with 3 stages that predicts the output of a XOR FUNCTION

Primary LanguageSystemVerilog

svANN_VLSI

The following is a VLSI neural network with 3 stages that predicts the output of a XOR FUNCTION. final chip

basic diagram

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here you can see the three layers firing up one after the other

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here are the bias_functinons that folow ready-en protocol alt text this is the output of the Neurons for similicity i have set the operations to add so you can see here that 1+1+1+3 and so on alt text

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this is the master FSM Block diagram alt_text