sidjos

VipramMezzFirmware

Cache_Design_Project

Simple Cache Design Implementation in VHDL

cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

hls4ml

Machine learning in FPGAs using HLS

mlrefined

Python and MATLAB code examples and demos from the textbook "Machine Learning Refined" (Cambridge University Press). See our blog https://jermwatt.github.io/mlrefined/index.html for interactive versions of many of the notebooks in this repo.

NU_DSN_17

Lecture on Developing a (Basic) Machine Learning Workflow

Single_Cycle_Datapath

Single Cycle Datapath Processor

VIPRAM_Standard_Tests

Vertically Integrated Pattern Recognition Associative Memory Standard Tests.

VipramMezzFirmware

wavedrom

:ocean: Digital timing diagram rendering engine

sidjos/Cache_Design_Project

Simple Cache Design Implementation in VHDL

sidjos/Single_Cycle_Datapath

Single Cycle Datapath Processor

sidjos/VipramMezzFirmware

sidjos/wavedrom

:ocean: Digital timing diagram rendering engine

sidjos/cacti

An integrated cache and memory access time, cycle time, area, leakage, and dynamic power model

sidjos/hls4ml

Machine learning in FPGAs using HLS

sidjos/mlrefined

Python and MATLAB code examples and demos from the textbook "Machine Learning Refined" (Cambridge University Press). See our blog https://jermwatt.github.io/mlrefined/index.html for interactive versions of many of the notebooks in this repo.

sidjos/NU_DSN_17

Lecture on Developing a (Basic) Machine Learning Workflow

sidjos/VIPRAM_Standard_Tests

Vertically Integrated Pattern Recognition Associative Memory Standard Tests.

sidjos/OpenROAD-flow-scripts

sidjos/playlist-viz

Visualize audio features of a playlist's songs using Spotify Web API