sifferman

calculator

This project serves as a recreation of the chip-on-board found in most basic 8-digit calculators.

ESspice

Ethan Sifferman's Spice Simulator! Supports DC and Transient analysis of Resistors, Capacitors, Inductors, and MOSFETs.

flip_flop_visualizer

Website to visualize the timing and schematics of flip-flops.

fpga_screensaver

This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.

fusesoc_template

Example of how to get started with olofk/fusesoc.

labs-with-cva6

Advanced Architecture Labs with CVA6

schematics

Examples of how to Generate Schematics from SystemVerilog Synthesis Tools

tangnano_example

Simple example of how to get started with the Tang Nano with FuseSoC.

thesis

Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

mapache64

Custom 6502 Video Game Console

sifferman/labs-with-cva6

Advanced Architecture Labs with CVA6

sifferman/calculator

This project serves as a recreation of the chip-on-board found in most basic 8-digit calculators.

sifferman/sky130_schematics

sifferman/thesis

Ethan Sifferman Master's Thesis: "Advancing Synthesizable Verilog/SystemVerilog Education with Open-Source Tools and Autograders"

sifferman/cse121_labs

sifferman/verilator_example

sifferman/commercial_tools

Build Scripts for Commercial SystemVerilog Tools

sifferman/nes_controller_interface

NES Controller Interface written in Verilog-2005

sifferman/ESspice

Ethan Sifferman's Spice Simulator! Supports DC and Transient analysis of Resistors, Capacitors, Inductors, and MOSFETs.

sifferman/flip_flop_visualizer

Website to visualize the timing and schematics of flip-flops.

sifferman/basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

sifferman/cards

sifferman/CLI11

CLI11 is a command line parser for C++11 and beyond that provides a rich feature set with a simple and intuitive interface.

sifferman/common_cells

Common SystemVerilog components

sifferman/cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

sifferman/espresso_test

sifferman/flip_flop_example

sifferman/fpnew_sv2v

sifferman/muxes

sifferman/riscv-assembler

RISC-V Assembly code assembler package for Python.

sifferman/rustyperalta.github.io

sifferman/shadowbox

sifferman/sky130_netlistsvg

This project creates transistor schematics for the sky130 PDK.

sifferman/structs

Examples of how to use structures in IEEE 1800 SystemVerilog.

sifferman/submodule_test

sifferman/sv2v

SystemVerilog to Verilog conversion

sifferman/tt09-subtractor

sifferman/verilator

Verilator open-source SystemVerilog simulator and lint system

sifferman/vivado_ddr

sifferman/xschem_3d