Pinned Repositories
lambdalib
Hardware abstraction library
lambdapdk
Library of open source Process Design Kits (PDKs)
logik
A configurable RTL to bitstream FPGA toolchain
logiklib
Library of FPGA architectures
sc-education
Educational material
sc-leflib
sc-rfcs
RFCs for changes to SiliconCompiler
scgallery
SiliconCompiler Design Gallery
siliconcompiler
Modular hardware build system
zerosoc
Demo SoC for SiliconCompiler.
siliconcompiler's Repositories
siliconcompiler/siliconcompiler
Modular hardware build system
siliconcompiler/zerosoc
Demo SoC for SiliconCompiler.
siliconcompiler/logik
A configurable RTL to bitstream FPGA toolchain
siliconcompiler/lambdapdk
Library of open source Process Design Kits (PDKs)
siliconcompiler/scgallery
SiliconCompiler Design Gallery
siliconcompiler/lambdalib
Hardware abstraction library
siliconcompiler/logiklib
Library of FPGA architectures
siliconcompiler/sc-rfcs
RFCs for changes to SiliconCompiler
siliconcompiler/sc-education
Educational material
siliconcompiler/sc-leflib
siliconcompiler/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
siliconcompiler/sc-surelog
siliconcompiler/caravel_wrapper_heartbeat_example
This repository is a clone of efabless' "caravel_user_project" template. It contains a netlist and GDS file produced by a SiliconCompiler build flow, in a format that allows the MPW pre-tapeout checks to be run on the design.
siliconcompiler/common_cells
Common SystemVerilog components
siliconcompiler/fossi-foundation.github.io
FOSSi Foundation Website
siliconcompiler/OpenROAD-flow-scripts
siliconcompiler/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX