Pinned Repositories
Beagle_SDR_GPS
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
CLA_check
Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
DSP-RTL-Lib
RTL Verilog library for various DSP modules
fpga-fft
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
gnsssdr
Automatically exported from code.google.com/p/gnsssdr
gps-sdr-sim
Software-Defined GPS Signal Simulator
inductor-generator
inkscapeCircuitSymbols
Inkscape extension to assist creating circuit symbols.
meep
free finite-difference time-domain (FDTD) software for electromagnetic simulations
siliziumcircuits's Repositories
siliziumcircuits/Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
siliziumcircuits/Beagle_SDR_GPS
KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
siliziumcircuits/CLA_check
siliziumcircuits/DSP-RTL-Lib
RTL Verilog library for various DSP modules
siliziumcircuits/fpga-fft
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
siliziumcircuits/gnsssdr
Automatically exported from code.google.com/p/gnsssdr
siliziumcircuits/gps-sdr-sim
Software-Defined GPS Signal Simulator
siliziumcircuits/inductor-generator
siliziumcircuits/inkscapeCircuitSymbols
Inkscape extension to assist creating circuit symbols.
siliziumcircuits/meep
free finite-difference time-domain (FDTD) software for electromagnetic simulations
siliziumcircuits/OpenSERDES
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
siliziumcircuits/pinout
An open source Python package that generates hardware pinout diagrams as SVG images.
siliziumcircuits/pyMOSChar
Python port of Prof. Boris Murmann's gm/ID Starter Kit
siliziumcircuits/Qucs-RFlayout
Export Qucs RF schematics to KiCad layouts & OpenEMS scripts
siliziumcircuits/r22sdf
Pipeline FFT Implementation in Verilog HDL
siliziumcircuits/RTKLIB
siliziumcircuits/Silice
Silice is an open source language that simplifies prototyping and writing algorithms on FPGA architectures.
siliziumcircuits/sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
siliziumcircuits/tbgen
Generate testbench for your verilog module.
siliziumcircuits/terosHDL
The goal of TerosHDL is make the FPGA development easier and reliable. It is a powerful open source IDE.