simone-machetti
RTL Design Engineer | PhD Student at EPFL
Embedded Systems Laboratory, EPFLLausanne, Switzerland
Pinned Repositories
x-heep-femu
X-HEEP-based FPGA EMUlation Platform (FEMU).
x-heep-femu-sdk
X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK).
awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs.
axi-modules
AXI SystemVerilog IP modules.
black-parrot
A Linux-capable RISC-V multicore for and by the world.
cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6.
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more.
firesim-nvdla
FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud.
gpgpu
General-purpose graphics processing unit (GPGPU) design for machine-learning (ML) applications.
x-heep
simone-machetti's Repositories
simone-machetti/gpgpu
General-purpose graphics processing unit (GPGPU) design for machine-learning (ML) applications.
simone-machetti/x-heep
simone-machetti/awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs.
simone-machetti/axi-modules
AXI SystemVerilog IP modules.
simone-machetti/black-parrot
A Linux-capable RISC-V multicore for and by the world.
simone-machetti/cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6.
simone-machetti/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more.
simone-machetti/firesim-nvdla
FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud.
simone-machetti/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
simone-machetti/hw-nvdla
RTL, Cmodel, and testbench for NVDLA.
simone-machetti/i2c-fpga
Verilog I2C interface for FPGA implementation.
simone-machetti/mcpat
An integrated power, area, and timing modeling framework for multicore and manycore architectures.
simone-machetti/obi2axi
OBI to AXI bridge.
simone-machetti/opentitan
OpenTitan: Open source silicon root of trust.
simone-machetti/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU.
simone-machetti/pocl-vortex
a clone of POCL that includes RISC-V newlib devices support and Vortex
simone-machetti/pulp
This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.
simone-machetti/pulp_soc
pulp_soc is the core building component of PULP based SoCs.
simone-machetti/pulpino
An open-source microcontroller system based on RISC-V.
simone-machetti/pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
simone-machetti/pynq
Python Productivity for ZYNQ.
simone-machetti/riscv-v-spec
RISC-V V extension proposal.
simone-machetti/rocket-chip
Rocket Chip Generator.
simone-machetti/serv
SERV - The SErial RISC-V CPU.
simone-machetti/tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up.
simone-machetti/tutorial-template
Template for the Read the Docs tutorial.
simone-machetti/vortex