DI0/1 jitter, pulldown
jordens opened this issue · 5 comments
I would like to use DI0/1 for accurate and low-jitter timestamping and limiting. Currently it's a plain digital buffer driven from 3V3 digital and limited by the stability of that power supply, without hysteresis, requiring 1V/10ns slew rate.
Maybe we can give it a better supply/threshold and consider a 1V-threshold Schmitt trigger.
And we should add a pull-down.
I don't think this should become a zero-crossing detector. That wold make it useless for digital inputs.
@jordens what about such a circuit?
I added TVS protection, output buffer that can be disabled, Schmitt input.
I don't know if LVC14 is precise enough. We can use fast comparators like ADCMP600 or something cheaper
LVC14 has 0.6/0.9V thresholds
That circuit looks fine to me.
Should the Tvs be after or before the 51R?
TVS absorbs the energy. It gives a chance to the next chip to survive. 51R is to reduce the current in case ESD was really high.