sinasoltani123/32-bit-pipelined-MIPS-processor-implemented-using-Verilog-with-booth-multiplication-algorithm
32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite
Verilog
32-bit pipelined MIPS CPU using Verilog with booth multiplication algorithm (faster multiplication in hardware). Xilinx Sesign Suite
Verilog