Pinned Repositories
awesome-electronics
A curated list of awesome resources for electronic engineers and hobbyists
awesome-robotics
A list of awesome Robotics resources
caravel_sirius
core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Cores-SweRV
SweRV EH1 core
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Dual-Core-RISC-V-Processor
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
fpga-pid
Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
siriusm46's Repositories
siriusm46/Dual-Core-RISC-V-Processor
A dual core RISC-V processor (using PULP platform SoC) implemented on a Digilent Arty S7-50 FPGA board.
siriusm46/caravel_sirius
siriusm46/Cores-SweRV
SweRV EH1 core
siriusm46/MIPS-CPU-fork
A Simulative MIPS CPU running on Logisim.
siriusm46/tinytapeout_calculator
siriusm46/wbspi
A collection of SPI related cores
siriusm46/awesome_photonics
😎 curated list of open source photonics projects
siriusm46/adc_block_ram_spi_top
Xilinx Artix-7 FPGA design using block ram, XADC and a SPI slave (SCARF). The block ram is dual port and can be written by either SPI or XADC samples, and only read by SPI.
siriusm46/awesome
A curated list of awesome resources for HDL design and verification
siriusm46/awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs
siriusm46/AXI-protocol-Interconnect-Design-and-Implementation-
siriusm46/AXI4_Master_Interconnect_Slave
A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
siriusm46/AXI4Bus
一套AXI4 interconnect 组件，通过简单连接可以搭建需要的AXI interconnect。
siriusm46/cmod_a7_spi_sram
SPI slave to External SRAM interface for Cmod A7
siriusm46/esnet-fpga-library
ESnet general-purpose FPGA design library.
siriusm46/FPGA_MCU_SPI_COM
Simple SPI-based communication between FPGA and MCU, using EP4CE15 and STM32F407 as an example
siriusm46/fpga_screensaver
This project implements the VGA protocol and allows custom images to be displayed to the screen using the Sipeed Tang Nano FPGA dev board.
siriusm46/meep
free finite-difference time-domain (FDTD) software for electromagnetic simulations
siriusm46/OpenFASOC
Fully Open Source FASOC generators built on top of open-source EDA tools
siriusm46/QuadSPI
RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.
siriusm46/SiPANN
Artifical Neural Networks for use with Quantum Photonics
siriusm46/spi-master
SPI Master for FPGA - VHDL and Verilog
siriusm46/spi-to-axi-bridge
An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
siriusm46/spi_slave_simple
Simple System Verilog implementation of SPI Slave
siriusm46/SPIglass
A fully synthesizable, BRAM backed SPI Flash device
siriusm46/tinytapeout_bcd_decimal
siriusm46/verilog-axi
Verilog AXI components for FPGA implementation
siriusm46/verilog-uart
Verilog UART
siriusm46/VLSI-Project-AXI-to-APB-Bridge
siriusm46/vscode-hyhdl
VScode extention: instantiation, testbench, documentation for verilog