/axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

Primary LanguageSystemVerilogOtherNOASSERTION

AXI

CI status GitHub tag (latest SemVer) SHL-0.51 license

This is the implementation of the AMBA AXI protocol developed as part of the PULP platform at ETH Zurich. We implement AXI4+ATOPs and AXI4-Lite.

List of Modules

Name Description Doc
axi_atop_filter Filters atomic operations (ATOPs), i.e., write transactions that have a non-zero aw_atop value.
axi_burst_splitter Split AXI4 burst transfers into single-beat transactions.
axi_cdc AXI clock domain crossing based on a Gray FIFO implementation.
axi_cut Breaks all combinatorial paths between its input and output.
axi_delayer Synthesizable module which can (randomly) delays AXI channels.
axi_demux Demultiplexes an AXI bus from one slave port to multiple master ports. Doc
axi_dw_converter A data width converter between AXI interfaces of any data width.
axi_dw_downsizer A data width converter between a wide AXI master and a narrower AXI slave.
axi_dw_upsizer A data width converter between a narrow AXI master and a wider AXI slave.
axi_err_slv Always responds with an AXI decode/slave error for transactions which are sent to it.
axi_id_prepend This module prepends/strips the MSB from the AXI IDs.
axi_intf This file defines the interfaces we support.
axi_isolate.sv A module that can isolate downstream slaves from receiving new AXI4 transactions.
axi_join A connector that joins two AXI interfaces.
axi_lite_demux Demultiplexes an AXI4-Lite bus from one slave port to multiple master ports. Doc
axi_lite_join A connector that joins two AXI-Lite interfaces.
axi_lite_mailbox A AXI4-Lite Mailbox with two slave ports and usage triggered irq. Doc
axi_lite_mux Multiplexes AXI4-Lite slave ports down to one master port. Doc
axi_lite_regs AXI4-Lite registers with optional read-only and protection features. Doc
axi_lite_to_apb AXI4-Lite to APB4 protocol converter.
axi_lite_to_axi AXI4-Lite to AXI4 protocol converter.
axi_lite_xbar Fully-connected AXI4-Lite crossbar with an arbitrary number of slave and master ports. Doc
axi_modify_address A connector that allows addresses of AXI requests to be changed.
axi_multicut AXI register which can be used to relax timing pressure on long AXI buses.
axi_mux Multiplexes the AXI4 slave ports down to one master port. Doc
axi_pkg Contains AXI definitions, common structs, and useful helper functions.
axi_serializer Serializes transactions with different IDs to the same ID.
axi_test A set of testbench utilities for AXI interfaces.
axi_to_axi_lite AXI4 to AXI4-Lite protocol converter.
axi_xbar Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. Doc

Atomic Operations

AXI4+ATOPs means the full AXI4 specification plus atomic operations (ATOPs) as defined in Section E2.1 of the AMBA5 specification. This has the following implications for modules that do not implement ATOPs and systems that include such modules:

  • Masters that do not issue ATOPs must set aw_atop to '0.
  • Slaves that do not support ATOPs must specify this in their interface documentation and can ignore the aw_atop signal.
  • System designers are responsible for ensuring that
    1. slaves that do not support ATOPs are behind an axi_atop_filter if any master could issue an ATOP to such slaves and
    2. the aw_atop signal is well-defined at the input of any (non-AXI4-Lite) module in this repository.

Masters and slaves that do support ATOPs must adhere to Section E2.1 of the AMBA5 specification.