/VHDL

Repo for Digitale Systemen - VHDL

Primary LanguageVHDL

VHDL Repo

VHDL Repo

  • Lattice Directory with small demo for Lattice FPGA (Upduino v2.0 Lattice UltraPlus FPGA hardware)
  • MiniZED Directory with demo's for the Avnet Minized Board (Xilinx Zynq Z7007S)
  • Multisim Directory with demo's on howto generate VHDL from Multisim
  • PynqZ2 Directory with demo's for Pynq-Z2 Board (Xilinx ZYNQ XC7Z020-1CLG400C)
  • by Vincent Claes