Smartbench

Pinned Repositories

hdl
Smartbench project - FPGA HDL (Verilog)
Language:Verilog10
input_stage
Language:AGS Script0 3 10
mainboard
Smartbench Project - Mainboard (KiCad)
Language:Python2 3 92
software
Smartbench Project - Software (Python)
Language:Python1 3 11
tools
Language:C00

Smartbench's Repositories

smartbench/mainboard
Smartbench Project - Mainboard (KiCad)
Language:Python2 3 92
smartbench/hdl
Smartbench project - FPGA HDL (Verilog)
Language:Verilog10
smartbench/software
Smartbench Project - Software (Python)
Language:Python1 3 11
smartbench/input_stage
Language:AGS Script0 3 10
smartbench/tools
Language:C00