VHDL for Noobs

Introduction

This repository contains a few VHDL code samples for various logic devices commonly used in FPGA-based digital design. Refer to these examples as a starting point for comprehending and implementing logic circuits in VHDL on FPGA platforms.

Usage

Vivado Projects

The Vivado Projects directory contains Vivado 2023.1 project files.
Open the .xpr files in Vivado to run simulations and view synthesis schematics.

Raw VHDL

The Raw VHDL directory contains just the extracted VHDL code from the main projects and their testbenches for quick reference.
You can use these files in any other VHDL environment, such as Xilinx ISE 14.7, ModelSim, Altera, Cadence etc.

Pro Tips:

Coding VHDL in Notepad++ >> Coding VHDL in Vivado
VS Code features some nice VHDL plugins
Save Your Eyes in Vivado
VHDL Formatter
VHDL Testbench Template Generator
Tabs to Spaces Converter

Learn:

FPGA 4 Student
All About FPGA