Pinned Repositories
allmotion
Analysis_TCP_in_Linux
controls-wiki
Wiki for beamline controls at NSLS-II.
device-tree-xlnx
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
epics-eurothermModBus
EPICS-re2c
EPICS build rules for re2c
exercise
exercise for nndl
germ_agent
germDaemon
An EPICS IOC for Germainum UDP data streaming.
linux-xlnx
The official Linux kernel from Xilinx
solofrain's Repositories
solofrain/device-tree-xlnx
Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)
solofrain/linux-xlnx
The official Linux kernel from Xilinx
solofrain/allmotion
solofrain/Analysis_TCP_in_Linux
solofrain/controls-wiki
Wiki for beamline controls at NSLS-II.
solofrain/epics-eurothermModBus
solofrain/germ_agent
solofrain/germDaemon
An EPICS IOC for Germainum UDP data streaming.
solofrain/googlefinance
Python module to get real-time stock data from Google Finance API
solofrain/harvard
solofrain/harvardSyringe
EPICS support for Harvard Syringe pumps.
solofrain/hdl
HDL libraries and projects
solofrain/Hera-384
EPICS code for the new multi-element detectors at NSLS-II
solofrain/leetcode-master
《代码随想录》LeetCode 刷题攻略：200道经典题目刷题顺序，共60w字的详细图解，视频难点剖析，50余张思维导图，支持C++，Java，Python，Go，JavaScript等多语言版本，从此算法学习不再迷茫！🔥🔥 来看看，你会发现相见恨晚！🚀
solofrain/modern-cpp-features
A cheatsheet of modern C++ language and library features.
solofrain/motorZynq
solofrain/nndl.github.io
《神经网络与深度学习》 Neural Network and Deep Learning
solofrain/Octave
solofrain/pmac-motor-opi
Create opi file(s) for all motors controlled by Turbo PMAC in a beamline.
solofrain/procSvrCtrlIOC
Create an IOC for procServerControl.
solofrain/PYNQ
Python Productivity for ZYNQ
solofrain/pynq-tutorial
solofrain/pynq-z1_board_files
PYNQ-Z1 board files for Vivado
solofrain/pynq.github.io
An introduction to Pynq.
solofrain/qepro
solofrain/script
Various scripts.
solofrain/seabreeze
SeaBreeze library from Ocean Optics.
solofrain/u-boot-xlnx
The official Xilinx u-boot repository
solofrain/webopi
solofrain/xilinx_axidma
A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.