soobaanvlsi
Design and Verification Engineer, Specialized in Verilog, SystemVerilog, UVM Methodology
Elveego Circuits Pvt. Ltd.Bengaluru, India.
Pinned Repositories
100DaysOfRTL
100 Days of RTL
Absolute-Value-Finder
finding the Absolute Value
ahb2apb_bridge_vip
AHB to APB Bridge VIP
AMBA_AXI3
System Verilog and Emulation. Written all the five channels.
Asynchronous-FIFO
An FPGA implementation of Cummings' Asynchronous FIFO
awesome-iggly
A curated list of awesome warez and piracy links
cic_core
CIC-filter core
e203_hbirdv2
The Ultra-Low Power RISC-V Core
tinyriscv
A very simple and easy to understand RISC-V core.
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
soobaanvlsi's Repositories
soobaanvlsi/e203_hbirdv2
The Ultra-Low Power RISC-V Core
soobaanvlsi/tinyriscv
A very simple and easy to understand RISC-V core.
soobaanvlsi/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
soobaanvlsi/100DaysOfRTL
100 Days of RTL
soobaanvlsi/Absolute-Value-Finder
finding the Absolute Value
soobaanvlsi/ahb2apb_bridge_vip
AHB to APB Bridge VIP
soobaanvlsi/AMBA_AXI3
System Verilog and Emulation. Written all the five channels.
soobaanvlsi/Asynchronous-FIFO
An FPGA implementation of Cummings' Asynchronous FIFO
soobaanvlsi/awesome-iggly
A curated list of awesome warez and piracy links
soobaanvlsi/cic_core
CIC-filter core
soobaanvlsi/e200_opensource
The Ultra-Low Power RISC Core
soobaanvlsi/Fooocus
Focus on prompting and generating
soobaanvlsi/github-flash1
soobaanvlsi/hbird-sdk
OpenSource HummingBird RISC-V Software Development Kit
soobaanvlsi/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
soobaanvlsi/minerva
A 32-bit RISC-V soft processor
soobaanvlsi/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
soobaanvlsi/riscv-formal
RISC-V Formal Verification Framework
soobaanvlsi/riscv-test-env
soobaanvlsi/riscv-tests
soobaanvlsi/UART
UART design in SV and verification using UVM and SV