spdy1895

Passionate about digital system design, FPGA, hardware accelerators and SoC design. Currently learning hardware for computational Neuroscience.

studenntINDIA

Pinned Repositories

clock_multiplexed_FIFO
Language:Verilog0 1 01
cpp_repo
cpp for hardware synthesis(HLS).
Language:C++0 1 00
hdl_repo
this repo contains hdl codes for digital circuits.
Language:Verilog1 1 01
python_scripting
Language:Python0 1 00
RTL_synthesis_using_sky130
Language:Verilog5 1 03
spdy1895
0 1 00
sv_hdl
Language:SystemVerilog0 1 01
Systolic_Array
a matrix multiplication hardware consisting of processing elements and mac unit.
Language:Verilog1 1 01

spdy1895's Repositories

spdy1895/RTL_synthesis_using_sky130
Language:Verilog5 1 03
spdy1895/hdl_repo
this repo contains hdl codes for digital circuits.
Language:Verilog1 1 01
spdy1895/Systolic_Array
a matrix multiplication hardware consisting of processing elements and mac unit.
Language:Verilog1 1 01
spdy1895/clock_multiplexed_FIFO
Language:Verilog0 1 01
spdy1895/cpp_repo
cpp for hardware synthesis(HLS).
Language:C++0 1 00
spdy1895/python_scripting
Language:Python0 1 00
spdy1895/spdy1895
0 1 00
spdy1895/sv_hdl
Language:SystemVerilog0 1 01