I have absolutely no clue what I'm doing, but lets build a RISC-V core off this documentation.
blocks below are straight from slide 48, may need to reasses if all of it is needed for our goals (what are the goals anyways?). May need to add various glue components. TBD.
Thing | Status |
---|---|
Program Counter | done |
PC Mux | 50% |
RegFile | 75% ? |
Instruction Mem (or magic mem) | 0% |
ALU | 0% |
Op2sel Mux | 0% |
Op2Sel Mux | 0% |
JumpRegTargGen | 0% |
BranchTargGen | 0% |
JumpTargGen | 0% |
IType Sign Extend | 0% |
SType Sign Extend | 0% |
UType | 0% |
Decoder | 0% |
Reg File (last block on right) | 0% |
Data mem | 0% |
- How to create realistic tests, load magic memory with risc-v compiled instructions?
- use these tests somehow, compile, load ingto memory
- cocotb
- icarus verilog simulator for simulating verilog
- gtkwave for viewing waveforms from simulation
- python
contains all the verilog for the risc-v core.
contains all the cocotb test benches to test each module in the core
All test contain a make file which can be run by simply typing make