The repository shows the 5 - day wrokshop for beginners using open source tools like yosys,magic,opentimer,qrouter and the purpose of this repository is to provide a complete idea about the 5 - days workshop on VLSI SoC/Physical design using open source EDA tools.
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Day 1 - Study and Review Various Components of RISC-V based PicoSoC
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Day 2 - Chip Planning Strategies and Introduction to Foundry Library Cells
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Day 3 - Design and Characterize one Library Cell using magic Layout Tool and ngspice
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Day 4 - Pre-Layout Timing Analysis and Importance of Good Clock Tree
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Day 5 - Final Steps for RTL2GDS
IC TERMINOLOGIES :
Package QFN - 48 is manufactured by germany labs. The full form of QFN is Quad Flat No leads and the number 48 represents the number of ports of the chip.The package dimensions are 7mm * 7mm.
QFN - 48
Pads are one of the important components of the chip, which is used to send the signals to inside the chip and receive the signals from inside to outside and viceversa. core is a section of chip where we place the all digital components. A Die is a small block of semiconducting material on which a given functional circuit is fabricated.
RISC - V OVERVIEW:
1.RISC - V available in various flavours i.e genealogy
2.RV32 has 32 - bit instructions
- Suffixes specify available extensions -I : basic integer instruction set; -M : hardware mulptiplier/divider; -C : compressed instruction set (16 - bit)
PICORV32 OVERVIEW:
key features: 1. small size 2.high clock speed 3.native memory interface 4.optional IRQ support
IC DESIGN COMPONENTS:
Logic synthesis - yosys open synthesis suite
Floorplanning, Placement and CTS - graywolf
Routing - qrouter
Static Timing Analysis - opentimer
pre-layout/post-layout simulation - ngspice
schematic editor - esim
ngspice - General purpose circuit simulation programs for both non linear and linear analysis.
magic - Vlsi layout editor, extraction and DRC tool
opentimer - Open sourece high performance timing analysis tool
esim - Complext circuit design, SPICE simulation and analysis and PCB design
qflow - Tool chain for complete RTL2GDS flow
DAY1 LAB SKILLS:
yosys is synthesis tool which is used to convert the rtl code into gate level netlist. To open the yosys tool, we use the command yosys.
“which” is command used to shows the loction/directory path of tool/folder.Linux which command is used to identify the location of a given executable that is executed when you type the executable name (command) in the terminal prompt. The command searches for the executable specified as an argument in the directories listed in the PATH environment variable.
==> git clone is a Git command line utility which is used to target an existing repository and create a clone, or copy of the target repository.
==> The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory in various operating systems. It can be used in shell scripts and batch files.cd vsdflow command is usedchange the directory to vsdflow folder../vsdflow spi_slave_design_details.csv is to initialize the design.The ls command lists the contents of a specified directory, excluding dotfiles. If no directory is specified then, by default, the contents of the current directory are listed. Listed files are sorted alphabetically.ls -ltr outdir_spi_slave | wc will show you the total 17 number of lines beacuse 1st line will give total number and the rest 16 are the number of flies.
cd outdir_spi_slave command change the directory to outdir_spi_slave and the qflow display spi_slave command open and display the qflow manager where you do preference,synthesis,placement and so on.Qflow(complete tool chain) is a complete tool chain for synthesizing digital circuits starting from verilog source and ending in physical layout for a specific target fabrication process
These commands open two windows 1.layout window 2. Tkcon window
1st select the chip area and then type the command box in tkcon window.it shows the selected area in microns.
cd vsdflow is a command change the directory to vsdflow, mkdir is a command create the folder, cd my_picorv32 is a command to change the directory to my_picorv32, mkdir source synthesis layout is a command to create folders source, synthesis and layout, cp ~/vsdflow/Verilog/picorv32.v/source/. - copy the Verilog file i.e picorv32 from source to vsdflow, qflow gui &- it open qflow manager in a graphical user interface.
These commands open qflow manager window
set technology = osu018
Verilog source = picorv32.v
Verilog module = picorv32
What is the % ratio of flipflop/total logic ?
After entering the commands shown above, it opens a qflow manager and we set the preferences,technology = osu018, Verilog source = picorv32 and verilog module = picorv32. Click on start button opposite the preparation. If it is okay, then proceed to synthesis. Click on okay opposite to synthesis, it opens a synthesis log file. Synthesis file shows the number of cells, number of flops and etc.
Ratio of flops to logic cells = Total number of flops / Total number of cells
Number of cells = 13197
Number of flops = 1613
Ratio of flops to total logic = 1317/1613 = 12.22%
core is the section of the chip where the fundamental logic of the design is placed. Adie ,which consists of core ,is a small semiconductor material specimen on whcih the fundamental circuit is fabricated. A ** netlist** describes the connectivity of a electronic design.
If the logic cells occupies the complete area of the core,then this is called as 100% utilization. The Utilization Factor is defined as the ratio of area occupied by netlist to total area of the core. 100% utilization means utilization factor is 1.0.In practical scenario, we can only use 60 - 70 % utilization.
utilization factor = area occupied by netlist/Total area of the core
aspect ratio is defined as ratio of height to width of the core. If the aspect ratio is 1 then the chip is in square shape and if it is 0.5 then the chip is in rectangle shape.
Aspect ratio = height of the core / width of the core
Define locations of preplaced cells:
===> The arrangement of these IP's/blocks in a chip is reffered as floorplanning
===> Pre placed cells - These blocks have user defined locations and hence are placed in chip before automated placement and routing and are called as pre-placed cells.Examples of preplaced cells are memories,mux,multiplier etc. once there placed,it can't be touched by placement and routing tools. Automated placement and routing tool places the remaining logical cells in the design onto chip.
===> The prepalced cells has been placed in the core, depending upon the design scenario. Foe example,preplaced cells have more input connections then they are placed near to input side.
surround preplaced cells with decoupling capacitors:
===> During switching operatons, the ckt demands swichting current i.e peak current (I peak).
===> Due to the presence of resistance and capacitance, ther will be a voltage drop acroos them and the voltage at node A would be vdd'(0.7 v instead of 1v) . If the voltage goes below the noise margin,the logic 1 at the output of the circuit wont be detected.
noise margin summary:
For any signal to be considered as logic 0 and logic 1 , it should be in the NML and NMH respectively.If there is a huge difference between the vdd and vdd' then it comes into undefined region in noise margin levels.
For this problem, we have a solution i.e adding decoupling capacitors parallel to the circuit.Every time the circuit switches, it draws currents from the decoupling cap, wheras RL network is used to refill the charge into decoulping capacitor.If there are any power hungry circuits in the design, we place the decoupling caps close to them physically.
POWER PLANNING: Decoupling caps take care of local communication but for global communication, we use power planning.
All the caps, which were charged to v volts will have to discharge to 0 through single ground point. This will cause a bump in groung tap point and it is called as ground bounce.All the caps, which were at 0 volts will have to charged to v through single power point. This will cause a bump in power tap point and it is called as votlage droop.
instead of single power supply, we will use multiple supplies so that we can avoid voltage droop and ground bounce.power planning can be done in mash shape.
PIN PLACEMENT and LOGIC CELL PLACEMENT BLOCKAGE: The connectivity info between gates is coded using VHDL/Verilog lang. and it is called as netlist. Pin placement is used the space between die and core. Frontend team defines the netlist connectivity and backend team defines the pin placement. Clock ports are bigger in size compared to data pins, the reason is clock is continuouslly driven the all flops in the design so we need least resistance as we know that resistance is inversely propotional to area.
LOGICAL CELL PLACEMENT BLOCKAGE: It blocks the particular area in between the die and core so that automated placement and routing tools can't be placed the logical cells into the area.The floorplan is ready for placement and routing.
PLACEMENT & ROUTING:
bind netlist with physical cells: Library has different flavours of gates/cells with different sizes, different threshold voltges and different timing information. once we are given proper size/shape to the gate/cell then we go for placement.
Placement: Placement is the process of determining the locations of circuit devices on a die surface.
Optimize placement based on estimated wire length and capacitance: This is the stage where we estimate wire length and capacitance ,based on that we place repeaters. To maintain signal integrity between the input ports to flops so we use repeaters in between them. Slew depend upon the vaule of the capacitance.The higher the value of cap, the amount of charge required to charge the cap will high because of that slew will be bad.
need for library and characterizaton: From RTL2GDSII, one thing is common for all stages i.e is library.All the standard cells being placed in a section is called library.It consists of different sizes/shapes of the gates,different functionality of the gates and differnet Vth (LVT,HVT,SVT) cells. Vth = 0.4v inverter takes more time to switch compare to vth = 0.3v inverter.
CELL DESIGN FLOW: It divided into 3 parts : 1. inputs 2. Design steps 3.outputs
1.Inputs: Process Design kit's,DRC & LVS,SPICE models,library and user definend specs.
DRC & LVS: Technology file provides the lambda rules. For example, polywidth should be 2λ or more than that.
λ = L/2 where L = min. feature size
llibrary and user defined specs:
cell height : The separaton between power rails and ground rails decides the cell height.
cell width : Cell width depends upon the timing info.if cell drive strength is lower, it's difficult for that cell to drive the huge wire length
power supply : A typical inverter has to operate at certain voltage which is provided by the top level designer.
2. circuit design stpes:
i. circuit design: 1.implement the function 2.model the design in order to meet the library requirements.
ii. layout design: art of layout is a combination of eluer,s path and stick diagram
1.function implemented into set of Pmos and nmos 2.get the pmos netwrok graph and nmos netwrok graph 3.get the euler's path and then draw stick diagram 4.draw layout 5.extraxt spice model which consist the info of parasitics (R,C)
3.Characterization: It is the step that will help to get the info of timing,noise and power.GUNA tool is used for timing,noise and power characterization.
TIMINIG CHARACTERIZATION: Timing and delay information is important to the ASIC design process because it allows a level of realism to be incorporated into the circuit model.
propagation delay: Propagation delay typically refers to the rise time or fall time in logic gates. This is the time it takes for a logic gate to change its output state based on a change in the input state. It occurs due to inherent capacitance in the logic gate.
tp = time(out_*_thr) - time (in_*_thr)
choosing threshold points is very important. If we haven't take care this, propagation delay will be -ve.There are 2 situations for tp = -ve, 1. if the threshold points are moved to above then tp is -ve and 2. if the circuit is designed not properly, it has hage wire delays then it leads to -ve propagation delay.
Transition delay: Transition delay or slew is defined as the time taken by signal to rise from 10 %( 20%) to the 90 %( 80%) of its maximum value.
DAY2 LAB SKILLS:
First we have to change the directory to vsdflow using the command cd vsdflow,and then make a directory name my_picorv32 using the command mkdir my_picorv32 then change the directory to my_picorv32 and mkdir source synthesis layout is a command to create folders source, synthesis and layout, cp ../Verilog/picorv32.v source/ - copy the Verilog file i.e picorv32.v, qflow gui &- it open qflow manager in a graphical user interface.
After entering the commands shown above, it opens a qflow manager and we set technology = osu018, Verilog source = picorv32 and verilog module = picorv32. Click on start button opposite the preparation. If it is okay, then proceed to synthesis. Click on okay opposite to synthesis, it opens a synthesis log file. Synthesis file shows the number of cells, number of flops and etc.
1st select the chip area and then type the command box in tkcon window.it shows the selected area in microns.
The below images shows the pins(clk,rstn) in bottom of chip.first we group them and then select the pin arrange to bottom.
The below image shows the chip area which is selected in the layoutsection.
1.SPICE deck Creation for CMOS Inverter:
SPICE Deck: it is the information of component connectivity,intput and output. substrate/body of pmos is connected to vdd and nmos substrate/body is conncted to vss.
component values :
M1:PMOS : W/L = 0.375u/0.25u
M2:NMOS : W/L = 0.375u/0.25u
cap : Cload = 10fF
vin = 2.5v and vdd = 2.5v
ideally,pmos should be twice/trice bigger than nmos.
SPICE Waveform: It is the transfer characteristics of the inverter.
SWITCHING THRESHOLD(Vm): Integrity and robustness,expressed by the static (or steady-state) behavior. CMOS Inverter robustness, defines certain parameters and one of thing is switching threshold. switching threshold (Vm) means the point at which the device switches.draw a tan 45 line in DC characteristic i.e vout vs vin.
Vm has a critical area because of 1. Vin = Vout 2.Both pmos and nmos arein the sat. region 3.if both nmos and pmos are turn on, there is a leakage current flow from power to gnd.The effect of changing the Wp/Wn ratio is to shift the transient region of the VTC. Increasing the width of the PMOS or the NMOS moves VM towards VDD or GND respectively.
Layout: Art of layout is a combination of euler's path and stick diagram.
using pull up network, we can build pull down network using duality theorem and demorgan's theorem.pull down network is complementary function of pull up network and thats where duality and demorgan's theorems comes into picture.
The function of the circuit f = ((A.C).(B+D) + (E.F))'
Layout using only stick diagram: These are the problems comes into picture, if we are only using stick diagram to draw a layout.
1. Congestion problem
2. DRC rule issues
3. Manufacturing issues
Layout diagram using Euler's path and stick diagram: stick diagram is a interface between circuit and final layout. Euler's path is defined as it is the path that covers each vertices atleast once. Optimize euler's path gives optimize layout.
Optimize euler's path A - C - E - F - D - B
Design Rules Check (DRC): Afte completion of the layout, you need to check the design rule. It is very important step for the post layout simulation and fabrication of a chip.
polywidth 2λ
metal width 3λ
poly to active spaceing 1λ
DAY3 LAB SKILLS
git clone is a Git command line utility which is used to target an existing repository and create a clone, or copy of the target repository and change the directory to ngspice using the command cd ngspice . ngspice is a tool which is used for circuit simulation.The cat command allows us to create single or multiple files, view contain of file, concatenate files and redirect output in terminal or files. The cat inv.spice is open the file of inverter which shows the netlist description of the inverter and also it shows the pmos and nmos width(Wp,Wn),length(Lp,Ln) and load capacitance value i.e used in the design.
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory in various operating systems. It can be used in shell scripts and batch files.cd ngspice_labs command changes the directory into ngspice_labs. ngspice is a circuit simulation tool used to simulate the dc and transient characteristics of different gates/cells.ngspice inv.spice command open the simulataion tool and the design is inverter.ngspice 1 -> run is used to run the fn_prelayout.spice. setplot tran1 is used to set the plot in dc mode. plot is a command, which is used to plot simulated waveforms with respect some input in this case input (50% of the power supply) i.e 1.25.This will open a plot with CMOS VTC and Blue 45 degree line
The below diagram shows the VTC characteristics of an inverter. The blueline(tan 45) intersecting the VTC curve that is called as switching threshold voltage(vm). swicthing threshold is the point where vin = vout and at which both p & n mos turned on and they are in saturation region.
By using leafpad inv.spice command opens the inv.spice file and then edit the pmos width into 0.75u and then perform the dc simulation in ngspice simulation tool.The below figure shows that cmos model description and the w/l ratios of both pmos and nmos.After changing the width of pmos,the transfer characteristic curve shifts to right side.
The below images shows the all the commands and switching threshold value(vm) i.e x0
The leafpad is a application which is used to open the files. ngspice is a circuit simulation tool used to simulate the dc and transient characteristics of different gates/cells.By using leafpad inv.spice command opens the inv.spice file and then edit the pmos width into 0.75u and then perform the dc simulation in ngspice simulation tool.The below figure shows that cmos model description and the w/l ratios of both pmos and nmos.After changing the width of pmos, ngspice 1 -> run is used to run the fn_prelayout.spice. setplot tran1 is used to set the plot in dc mode. plot is a command, which is used to plot simulated waveforms with respect some input in this case input (50% of the power supply) i.e 1.25.This will open a plot with CMOS VTC and Blue 45 degree line
The below images shows the all the commands, which are used to open the simulation
The below figure shows the values of input fall time at 50% of power supply (1st x0) and output rise time at 50% of power supply(2nd x0)
The below image shows the trainsient charecters of an inverter if input = 0v then output =2.5v(in this case) . it depends on the technolgy.
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory in various operating systems. It can be used in shell scripts and batch files. ngspice is a circuit simulation tool used to simulate the dc and transient characteristics of different gates/cells.Change the directory to ngspice_labs and then open simulation tool with the command - ngspice fn_prelayout.spice . ngspice 1 -> run is used to run the fn_prelayout.spice. setplot tran1 is used to set the plot in transient mode. plot is a command, which is used to plot simulated waveforms with respect some input in this case input (50% of the power supply) i.e 1.25.
The below figure shows the respective commands shown above:
The below figure shows the value of x0 at the intersection of horizontal blue line(50% of the power supply) and middle rising waveform (50% of power supply):
The below image shows transient waveform:
The below figure shows the value of x0 at the intersection of horizontal blue line(50% of the power supply) and middle rising waveform (50% of power supply):
The rise/fall time values of 10% and 90% are calculated based on an algorithm, which looks at the mean power above and below the 50% points of the rise/fall times. The pulse width is based on the 50% points in linear power (W) mode.
cd ngspice_labs is used the change the directory to ngspice_labs. magic is a tool which is used to construct the layout.Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit. source draw_fn.tcl is run the drwa_fn tcl file and it draw a layout for the function. The layout consist of polysilicon straps, n- well, metal contacts with width 3lambda and etc.
The below figure shows the command which are used to open magic tool with a technology file. The technology file consist of all the design rules that must be satisfy to draw a layout.
The blow image shows the layout diagram of a function. In the layout, the pink color strips are polysilicon strips and bottom of the layout shows the gnd terminal and it has contacts which are used to connect the ground terminal.
cd ngspice_labs is used the change the directory to ngspice_labs. magic is a tool which is used to construct the layout.Integrated circuit layout, also known IC layout, IC mask layout, or mask design, is the representation of an integrated circuit in terms of planar geometric shapes which correspond to the patterns of metal, oxide, or semiconductor layers that make up the components of the integrated circuit.The layout consist of polysilicon straps, n- well, metal contacts with width 3lambda and etc. The below figure shows the command which are used to open magic tool with a technology file. The technology file consist of all the design rules that must be satisfy to draw a layout.
The below figure shows the above commands which are used to open magic tool:
The below figure shows the layout of a function and select the whole to find the area of the design.
In tkcon window type box,after selecting the whole chip then only it shows the area of the design in microns.
After sourcing the draw_fn.tcl. we will extract all files and also spice files by using the commands extract all and eext2spice. From ther we fn.postlayout.spice, then this file is edited as it doesn't consists of vdd and gnd info. For the stimulus to obtain those were copied from the fn_layout and added to the fn_postlayout and then the simulation is done.
Extract all command is used to extract all parasitics and it creates a file name fn_postlayout.ext
The below figure shows the transient response:
1st x0 shows the rise time and 2nd x0 is the fall time of the above transient analysis:
Delay Table: At every level, Each buffer varies output load capacitance and input transitions/slew. in simple way, we have varying input transition at input buffer and varying output load at output load at the output buffer.so that we have different delays for one buffer/cell and solution for that is delay table. Delay Table is the representation of delays of a particular cell while varying the input slew and output load.
Timing Analysis:
setup timing analysis: The setup time is the interval before the clock where the data must be held stable.
hold timing analysis: The hold time is the interval after the clock where the data must be held stable. Hold time can be negative, which means the data can change slightly before the clock edge and still be properly captured.
Clock Tree Routing: It is very important setp for the performance. H - tree is used to build the clock tree. The main objective of clock tree routing is minimazation of the skew. In clock routing, we clock buffers. there is a differnce in clock buffer and normal buffer that clock buffer have equal rise and fall time but in case of normal buffer it's not.
cross talk: Crosstalk is a phenomenon, by which a logic transmitted in vlsi circuit or a net/wire creates undesired effect on the neighbouring circuit or nets/wires, due to capacitive coupling. If there is a crosstalk between two nets then all the parameters(input transition/slew ) are deteriorates.
Shielding: shielding is placing ground or power lines at the sides of a. victim signal line to reduce noise and delay uncertainty. clock nets are considered as critical nets, by shielding the clock net we will protect the clock net from the outside world.
DAY4 LAB SKILLS:
git clone is a Git command line utility which is used to target an existing repository and create a clone, or copy of the target repository and ngspice is a tool which is used for circuit simulation and change the directory to ngspice_labs.The cat command allows us to create single or multiple files, view contain of file, concatenate files and redirect output in terminal or files and cat inv_tran.spice- it open the inv_tran.spice file. The file contains the info of the pmos and nmos that is width,length and the input pulse signal shows the rise slew and fall slew values.
The below figure shows the netlist description of a inverter. in that image, vin is a pulse with time period = 2ns,pulse width = 1ns,rise and fall slew = 10ps.
The below figure shows the netlist description of a inverter. in that image, cload represents the load capacitance of 10fF.
The below figure shows the transient response of a inverter. from that, we calculate rise time delay. It is difference between rise time of output(1st x0) to fall time input(2nd x0).
git clone is a Git command line utility which is used to target an existing repository and create a clone, or copy of the target repository and ngspice is a tool which is used for circuit simulation and change the directory to ngspice_labs.The cat command allows us to create single or multiple files, view contain of file, concatenate files and redirect output in terminal or files and cat inv_tran.spice- it open the inv_tran.spice file. The file contains the info of the pmos and nmos that is width,length and the input pulse signal shows the rise slew and fall slew values. Leafpad used to open the file and then we change the load value to 20fF.
The image is after editing the output load capacitance.
It is the transient response of the inverter:
rise delay is difference between rise time of output(2nd x0) to fall time input(1st x0).
leafpad /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib opens the standard cell library with the technolgy of 180nm. The file will shows all info like slew_upper_thershold_pct_fall,output_threshold_pct_rise, various sizes of cells and their timing info.
The below figure shows the library file of 180nm technolgy. It contains all standard cells like and,or,inv,mux and etc.
What are the 2 variables of "delay_template_5x5"?
Which cell delay table in line number 2943?
Which delay template is used for INVX1?
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory and change the directory to vsdflow/my_picorv32. sta command is used to run the prelayout.conf file.
The leafpad picorv32.sdc is used to open picorv32.sdc . In sdc, we create a clock with period of 2.5ns with pulse width 1.25ns and the clock name is clk.
leafpad is used to open and then modify the contents with the below commands in prelayout_sta.conf. read_liberty /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib is command used to read the library file in the given path. read_verilog synthesis/picorv32.rtlnopwr.v is a command read the verilog file in the given path. read_sdc picorv32.sdc it reads the synopsys design constraints. report_checks it reports the timing info like slack,data arrival time and required time.
The below image shows the setup timing analysis. it shows the data rquired time, data arrival time and slack. slack is the difference to data requirerd time to data arrival time.
% report_checks -digits 4 is a command used to check the timing info with 4 digits.
What is the data arrival time and required time?
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory and change the directory to vsdflow/my_picorv32. sta command is used to run the prelayout.conf file.The leafpad picorv32.sdc is used to open picorv32.sdc . In sdc, we create a clock with period of 2.5ns with pulse width 1.25ns and the clock name is clk.leafpad is used to open and then modify the contents with the below commands in prelayout_sta.conf. read_liberty /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib is command used to read the library file in the given path. read_verilog synthesis/picorv32.rtlnopwr.v is a command read the verilog file in the given path. read_sdc picorv32.sdc it reads the synopsys design constraints. set_propagated_clock [all_clocks] is a command which set the clock propagates through all clocks. report_checks it reports the timing info like slack,data arrival time and required time.
What is the SLACK value after clock propagation ?
These are the commands which are used to open sta. Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations.
The below figure shows the slack after the propagation of the clock i.e post static timing analysis.
What is launch clock network delay or clock network delay propagated ?
What is the capture clock network delay?
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory and change the directory to vsdflow/my_picorv32. sta command is used to run the prelayout.conf file.The leafpad picorv32.sdc is used to open picorv32.sdc . In sdc, we create a clock with period of 2.5ns with pulse width 1.25ns and the clock name is clk.leafpad is used to open and then modify the contents with the below commands in prelayout_sta.conf. read_liberty /usr/local/share/qflow/tech/osu018/osu018_stdcells.lib is command used to read the library file in the given path. read_verilog synthesis/picorv32.rtlnopwr.v is a command read the verilog file in the given path. read_sdc picorv32.sdc it reads the synopsys design constraints. set_propagated_clock [all_clocks] is a command which set the clock propagates through all clocks. report_checks -path_delay min -digits 4 it reports the timing info like slack,data arrival time and required time of hold analysis.
What is library hold time and hold slack?
Setup and hold slack is defined as the difference between data required time and data arrival time. setup slack= Data Required Time - Data Arrival Time. hold slack= Data Arrival Time - Data Required Time.
Routing: In the vlsi design cycle, routing follows cell placement. To interconnect all the pins according to the specification of nets its konwn as routing. once routing is completed, precise paths are defined on the layout surface on which conductors carrying electrical signals are run. The main objective of routing is to minimize the area required for routing.
There are 3 types of routing:
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Grid/area routing
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Global routing
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Detailed routing
Design Rule Check: These design rules in the technology file. for every technology, the design rules changes.
There 3 typical design rules for the pairs of wires, which are running parallel.
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Wire Width : The wire has min. width or more than that is okay
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wire pitch: The centre to centre distance between 2 wires called as wire pitch.
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wire spacing: wire to wire maintain min.spacing or more than that
If signal short occur, we route one of the signal into another metal layer.
Parasitic Extraction:
Each and evry wire has got finite resistanc and capacitance and we have to extract it and then provides to analysis tool. Parasitic extraction represent in a special format known as SPEF Format. SPEF full form is Standard Parasitic Exchange Format
** SPEF : standard parasitic exchange format** IEEE 1481 - 1999
The above two lines are SPEF Header
DAY5 LAB SKILLS
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory and the current directory is /vsdflow/my_picorv32 and then start the routing for picorv32 using the command qflow route picorv32. After completing the 3 stages of routing,open sta for picorv32. BACKANNO -- Annotate the Subcircuit Pin Names to the Port Currents. ... raw file that can be used to refer to port currents by the pin name. This allows you to cross probe pin currents by clicking on the symbol's pin and then open the log file of sta for the design and it shows the pre-layout frequency
It is the max. frequency in prelayout and which is 313.676MHz
The cd command, also known as chdir (change directory), is a command-line shell command used to change the current working directory and the current directory is /vsdflow/my_picorv32 and then start the routing for picorv32 using the command qflow route picorv32. After completing the 3 stages of routing,open sta for picorv32. BACKANNO -- Annotate the Subcircuit Pin Names to the Port Currents. ... raw file that can be used to refer to port currents by the pin name. This allows you to cross probe pin currents by clicking on the symbol's pin and then open the log file of sta for the design.without completion of routing the post layout frequency is not shown in the file.log/post_sta.log shows the maximum frequency of the postlayout.
It is the max. frequency in postlayout and which is 293.556MHz
ACKNOWLEDGEMENT:
- Kunal Ghosh Co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd.