Pinned Repositories
aragor-s-celestial-quest
LaTeX source files for my book "Aragor's Celestial Quest."
branch-coverage
BIL481 Assignment 2
BuildExecutable.jl
Build a standalone executables from a Julia script
circt
Circuit IR Compilers and Tools
city
2016-2017 Spring BIL 214 Homework 3
clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
d3d11-engine
D3D11 Experimental an old project imported from Bitbucket
riscv32-cosim-model
RISC-V processor co-simulation using SystemVerilog HDL and UVM.
riscv32-sim
An easy-to-use, still-in-development RISC-V 32-bit instruction-accurate (IA) simulator.
ssayin's Repositories
ssayin/riscv32-cosim-model
RISC-V processor co-simulation using SystemVerilog HDL and UVM.
ssayin/riscv32-sim
An easy-to-use, still-in-development RISC-V 32-bit instruction-accurate (IA) simulator.
ssayin/aragor-s-celestial-quest
LaTeX source files for my book "Aragor's Celestial Quest."
ssayin/branch-coverage
BIL481 Assignment 2
ssayin/circt
Circuit IR Compilers and Tools
ssayin/city
2016-2017 Spring BIL 214 Homework 3
ssayin/clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
ssayin/dataflow-architecture
ssayin/dumb-jose
Insecure library for an insecure format. GitHub mirror from https://gitea.treehouse.systems/jmercan/dumb-jose.
ssayin/etu-coursebase
etu-coursebase
ssayin/embench-iot
The main Embench repository
ssayin/espresso
ssayin/etu-tvl
Interpreter implementation for a three-valued logic language
ssayin/euro2016
2015-2016 Summer BIL 143 Homework 4
ssayin/gem5
The official repository for the gem5 computer-system architecture simulator.
ssayin/lua-astronomical-almanac
Lua bindings for Astronomical Almanac (AA) a.k.a Moshier Ephemeris.
ssayin/mimalloc
mimalloc is a compact general purpose allocator with excellent performance.
ssayin/nandgame-sv
Experimental
ssayin/null-ls.nvim
Use Neovim as a language server to inject LSP diagnostics, code actions, and more via Lua.
ssayin/ramulator2
Ramulator 2.0 is a modern, modular, extensible, and fast cycle-accurate DRAM simulator. It provides support for agile implementation and evaluation of new memory system designs (e.g., new DRAM standards, emerging RowHammer mitigation techniques). Described in our paper https://people.inf.ethz.ch/omutlu/pub/Ramulator2_arxiv23.pdf
ssayin/riscv-arch-test
ssayin/riscv-isa-sim
Spike, a RISC-V ISA Simulator
ssayin/riscv-opcodes
RISC-V Opcodes
ssayin/riscv32-decoder
A RISC-V instruction decoding library supporting 32-bit Integer (I), Multiply/Divide (M), Compressed (C), and Control and Status Register (Zicsr) instruction set extensions.
ssayin/riscv32-perf-model
ssayin/riscv32-sim-common
Shared data structures and utilities for decoding RISC-V instructions and exporting hart states across the riscv32-sim, riscv32-cosim-model, and riscv32-decoder projects.
ssayin/specni
An application which assesses planetary dignities/debilities based on Lilly's table given on p.115 of Christian Astrology
ssayin/ssayin
ssayin/vim-snippets
My snippets
ssayin/xv6-riscv
Xv6 for RISC-V