/USTC_2022FA_ICdesign

Design a micro chip in TSMC .18um process, including a mips cpu (8 bit) and a systolic array accelerator

Primary LanguageVerilog

Chip Design Practice 2022FA

This project is done and GDS map has been submitted to the foundry. We are waiting for the return of chips.

The working directory lies in ./ic_finish, including source codes, scripts and snapshots.