/211-Lab8

Primary LanguageVerilog

CPEN211-Lab7

TO-DO: [.] fix overflow flag in datapath.v

  • debug MOV error in autograder

  • stage 1: execute instructions from memory

    • lab7_top.v
    • 4 new states in FSM
  • stage 2: use memory to store data and instructions

    • 2 new instructions: LDR & STR
  • stage 3: load/ store using De1-SoC

    • design 2 CL circuits: 1 for LDR input, 1 for STR output