stevehoover

I am the founder of Redwood EDA. More on linkedin: https://www.linkedin.com/in/steve-hoover-a44b607/

Redwood EDA (@rweda, though most of our open source work is on gitlab)Massachusetts

Pinned Repositories

1st-CLaaS
Developing Smith Waterman accelerators on F1 instances using 1st CLaaS
Language:C5 0 02
immutable
Language:TL-Verilog3 1 01
LF-Building-a-RISC-V-CPU-Core
Language:TL-Verilog314 19 3173
LF-Building-a-RISC-V-CPU-Core-Course
The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.
Language:Python6 1 00
makerchip_examples
Language:TL-Verilog158
MYTH_Workshop_Assignments
Starting-point template for students in the Microprocessor for You in Thirty Hours Workshop
97
RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
Language:TL-Verilog76 9 131
VSDBabySoC
VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
Language:Verilog31
VSDOpen2020_TLV_RISC-V_Tutorial
For students of the VSDOpen2020 TL-Verilog RISC-V Tutorial
5 2 08
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Language:TL-Verilog224 25 956

stevehoover's Repositories

stevehoover/LF-Building-a-RISC-V-CPU-Core
Language:TL-Verilog314 19 3173
stevehoover/warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
Language:TL-Verilog224 25 956
stevehoover/RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
Language:TL-Verilog76 9 131
stevehoover/makerchip_examples
Language:TL-Verilog158
stevehoover/LF-Building-a-RISC-V-CPU-Core-Course
The Linux Foundation/Redwood EDA "Building a RISC-V CPU" Course content, also available via EdX.
Language:Python6 1 00
stevehoover/1st-CLaaS
Developing Smith Waterman accelerators on F1 instances using 1st CLaaS
Language:C5 0 02
stevehoover/immutable
Language:TL-Verilog3 1 01
stevehoover/warp-v_includes
A companion to /warp-v containing files that are included from /warp-v.
Language:Verilog32
stevehoover/conversion-to-TLV
A repository for exploring LLM-assisted code conversion to TL-Verilog.
Language:Python21
stevehoover/awesome-opensource-hardware
List of awesome open source hardware tools, generators, and reusable designs
Language:Python1
stevehoover/test
hooo
Language:TL-Verilog1 2 0
stevehoover/tt05-verilog-demo
Verilog Demo, updated for Tiny Tapeout 05
Language:Verilog1
stevehoover/chips-gsoc-ideas
stevehoover/efabless-tt-fpga-dl-demo-AES
Language:Verilog
stevehoover/efabless-tt06-verilog-template
Language:TL-Verilog
stevehoover/fossi-foundation-web
stevehoover/fossi-foundation.github.io
FOSSi Foundation Website
Language:HTML
stevehoover/makerchip_tool_for_efabless
Prepared for Efabless
stevehoover/MEST_Course
Content for MEST circuit design course.
1 0
stevehoover/moku_tlv_lib
TL-Verilog content for Liquid Instruments Moku products.
1 0
stevehoover/tlv-vscode
Language:TypeScript0 02
stevehoover/tt-fpga-demo
Language:Tcl
stevehoover/tt-fpga-hdl-demo
Language:Verilog1 0
stevehoover/tt-fpga-hdl-demo-tmp-test
Temporary -- DELETE ME
Language:TL-Verilog
stevehoover/tt-fpga-hdl-demo2
Language:Verilog
stevehoover/tt-mest-fpga-wokwi-template
Language:Tcl
stevehoover/tt06-my-proj
Language:TL-Verilog
stevehoover/tt06-tl-verilog-template
Submission template for Tiny Tapeout 06 - Verilog HDL Projects
Language:TL-Verilog
stevehoover/tt07-my-tl-verilog-project
Language:TL-Verilog
stevehoover/tt08-makerchip-template
Submission template for Tiny Tapeout 7 with a "makerchip" branch supporting Makerchip virtual lab and TL-Verilog
Language:TL-Verilog