Issues
- 0
- 2
vpi_put_value() at T0 is overridden
#1111 opened - 1
- 1
- 5
Support implicit named port connections
#1107 opened - 3
Add support for `assert( l_c === 1'b0 );` syntax
#1105 opened - 4
- 0
- 4
unsigned port connection sign extends
#1099 opened - 5
- 2
Override parameters in top-level Verilog
#1096 opened - 3
Question on AMS support
#1095 opened - 0
- 2
Support for "inside" statements
#1092 opened - 0
Improve error message in module instantiation when `wire` array given to `output` array with wrong lengths
#1091 opened - 1
- 7
- 5
- 0
- 3
The sv_parameter_type test hangs
#1083 opened - 5
The sv_literals test is not implemented
#1082 opened - 2
The sv_interface test is not implemented
#1081 opened - 2
- 2
array_packed_value_list test is not implemented
#1079 opened - 0
array_packed_sysfunct test is not implemented
#1078 opened - 15
OSSFuzz Integration
#1075 opened - 2
- 2
- 0
- 3
The Iverilog compiler lacks a warning message for mismatched port widths after compilation.
#1056 opened - 4
Undeclared signal - but it works!
#1053 opened - 8
- 0
github actions: The mingw32 run fails randomly
#1050 opened - 11
- 4
- 4
Iverilog hang on very large array of flops
#1046 opened - 1
Where is the grammar parsing done?
#1044 opened - 6
VPI: vpi_put_value() to a WIRE is not sticky.
#1041 opened - 1
Implement DPI support
#1040 opened - 0
94879487
#1039 opened - 5
- 4
vpiFullName does not include :: for packages
#1037 opened - 0
- 2
- 1
- 1
- 2
- 1
Support for Elaboration System Tasks
#1029 opened - 5
Icarus verilog makes no progress
#1028 opened - 2
Install error for v12.0
#1026 opened