Pinned Repositories
axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
berkeley-hardfloat
chisel-testers
Provides various testers for chisel users
chisel3
new firrtl based chisel
cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
darkstar
Radio astronomy lab group work
firrtl-interpreter
A scala based simulator for circuits described by a LoFirrtl file
HelloWorld
Sample Android project
hls4ml
Machine learning on FPGAs using HLS
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
stevobailey's Repositories
stevobailey/axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
stevobailey/berkeley-hardfloat
stevobailey/chisel-testers
Provides various testers for chisel users
stevobailey/chisel3
new firrtl based chisel
stevobailey/cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
stevobailey/darkstar
Radio astronomy lab group work
stevobailey/firrtl-interpreter
A scala based simulator for circuits described by a LoFirrtl file
stevobailey/HelloWorld
Sample Android project
stevobailey/hls4ml
Machine learning on FPGAs using HLS
stevobailey/ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
stevobailey/prysms
Python-based Real Yahoo Stock Market Simulator
stevobailey/splinter
splinter - python test framework for web applications
stevobailey/stevia
stevobailey/verilator
Verilator open-source SystemVerilog simulator and lint system
stevobailey/vicuna
RISC-V Zve32x Vector Coprocessor
stevobailey/website