stong/risc-uproc

Toy RISC microprocessor in Verilog for Altera FPGA

Unnamed Soft-core Microprocessor

I made this basic little CPU to learn about Verilog and FPGA, as well as basic processor design. Completed as part of coursework for CS 3220: Processor Design at Georgia Tech.

It features branch prediction and a very simple classic 5-stage RISC pipeline. Maybe one day I will add caches, data forwarding, and Tomasulo.