The NEORV32 Processor is a customizable microcontroller-like system on chip (SoC) that is based on the RISC-V NEORV32 CPU. The project is intended as auxiliary processor in larger SoC designs or as ready-to-go stand-alone custom / customizable microcontroller.
ℹ️ Want to know more? Check out the project's rationale.
📚 For detailed information take a look at the NEORV32 documentation (online at GitHub-pages). The doxygen-based documentation of the software framework is also available online at GitHub-pages.
🏷️ The project's change log is available in CHANGELOG.md.
To see the changes between official releases visit the project's release page.
📦 The setups folder provides exemplary setups targeting
various FPGA boards and toolchains to get you started.
🗒️ Check out the project boards for a list of current ideas, TODOs, features being planned and work-in-progress.
💡 Feel free to open a new issue or start a
new discussion if you have questions, comments, ideas or bug-fixes.
Check out how to contribute in CONTRIBUTE.md.
🚀 Check out the quick links below or directly jump to the User Guide to get started setting up your NEORV32 setup!
- CPU plus Processor/SoC plus Software Framework & Tooling
- completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
- fully synchronous design, no latches, no gated clocks
- be as small as possible (while being as RISC-V-compliant as possible) – but with a reasonable size-performance trade-off (the processor has to fit in a Lattice iCE40 UltraPlus 5k low-power FPGA running at 22+ MHz)
- from zero to
printf("hello world!");- completely open source and documented - easy to use even for FPGA/RISC-V starters – intended to work out of the box
The NEORV32 Processor (top entity: rtl/core/neorv32_top.vhd)
provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
to allow a flexible customization according to your needs. Note that all modules listed below are optional.
In-depth detailed information regarding the processor/SoC can be found in the 📚
online documentation - "NEORV32 Processors (SoC)".
Memory
- processor-internal data and instruction memories (DMEM / IMEM) & cache (iCACHE)
- bootloader (BOOTLDROM) with serial user interface
- supports boot via UART or from external SPI flash
Timers
IO
- standard serial interfaces (UART, SPI, TWI / I²C)
- general purpose GPIO and PWM
- smart LED interface (NEOLED) to directly drive NeoPixel(TM) LEDs
SoC Connectivity and Integration
- 32-bit external bus interface, Wishbone b4 compatible
(WISHBONE)
- wrapper for AXI4-Lite master interface
- alternative top entities/wrappers providing simplified and/or resolved top entity ports for easy system integration
- custom functions subsystem (CFS) for tightly-coupled custom co-processor extensions
Advanced
- true random number generator (TRNG)
- numerically-controlled oscillator (NCO)
- on-chip debugger (OCD) via JTGA - implementing the Minimal RISC-V Debug Specification Version 0.13.2 and compatible with the OpenOCD and gdb
ℹ️ It is recommended to use the processor setup even if you want to use the CPU in stand-alone mode. Simply disable all the processor-internal modules via the generics and you will get a "CPU wrapper" that already provides a minimal CPU environment and an external memory interface (like AXI4). This setup also allows to further use the default bootloader and software framework. From this base you can start building your own processor system.
ℹ️ Check out the setups
folder for exemplary setups targeting various FPGA boards.
ℹ️ The hardware resources used by the processor-internal IO/peripheral modules andmemories is also available in the online documentation - "NEORV32 Central Processing Unit".
Results generated for hardware version 1.4.9.0.
If not otherwise note, the setups use the default configuration (like no TRNG),
no external memory interface and only internal instruction and data memories
(IMEM uses 16kB and DMEM uses 8kB memory space).
| Vendor | FPGA | Board | Toolchain | CPU Configuration | LUT / LE | FF / REG | DSP (9-bit) | Memory Bits | BRAM / EBR | SPRAM | Frequency |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Intel | Cyclone IV EP4CE22F17C6N |
Terasic DE0-Nano | Quartus Prime Lite 20.1 | rv32imcu_Zicsr_Zifencei |
3813 (17%) | 1904 (8%) | 0 (0%) | 231424 (38%) | - | - | 119 MHz |
| Lattice | iCE40 UltraPlus iCE40UP5K-SG48I |
setups\radiant\UPduino_v3 |
Radiant 2.1 (LSE) | rv32imac_Zicsr |
5123 (97%) | 1972 (37%) | 0 (0%) | - | 12 (40%) | 4 (100%) | c 24 MHz |
| Xilinx | Artix-7 XC7A35TICSG324-1L |
Arty A7-35T | Vivado 2019.2 | rv32imcu_Zicsr_Zifencei + PMP |
2465 (12%) | 1912 (5%) | 0 (0%) | - | 8 (16%) | - | c 100 MHz |
📚 In-depth detailed information regarding the CPU can be found in the online documentation - "NEORV32 Central Processing Unit".
The CPU (top entity: rtl/core/neorv32_cpu.vhd)
implements the RISC-V 32-bit rv32 ISA with optional extensions. It is compatible to a subset of the
Unprivileged ISA Specification (Version 2.2)
and a subset of the Privileged Architecture Specification (Version 1.12-draft).
The CPU passes the official RISC-V architecture tests
(see riscv-arch-test/README).
NEORV32 is an official (see architecture ID) little-endian
two-stage (+ multi-cycle) RISC-V CPU with independent instruction/data bus interfaces, and multiple supported operating
modes / privilege levels: machine and optional user and debug_mode.
It supports the standard RISC-V machine interrupts (MTI, MEI, MSI) and 1 non-maskable interrupt as well as 16
fast interrupt requests as custom extensions. The CPU also supports all standard RISC-V exceptions
(instruction/load/store misaligned address & bus access fault, illegal instruction, breakpoint, environment call).
As a special "execution safety" extension, all invalid, reserved or malformed instructions will raise an illegal
instruction exception.
Currently, the following optional RISC-V-compatible ISA extensions are implemented (linked to the according
documentation section). Note that the X extension is always enabled.
RV32
[I/
E]
[A]
[C]
[M]
[U]
[X]
[Zfinx]
[Zicsr]
[Zifencei]
[PMP]
[HPM]
ℹ️ The B ISA extension has been temporarily removed from the processor.
See B ISA Extension project board.
📚 More details regarding exemplary FPGA setups including a listing of resource utilization by each SoC module can be found in the online documentation - "FPGA Implementation Results".
Implementation results for exemplary CPU configuration generated for an Intel Cyclone IV EP4CE22F17C6N FPGA using Intel Quartus Prime Lite 20.1 ("balanced implementation"). The timing information is derived from the Timing Analyzer / Slow 1200mV 0C Model. No constraints were used at all.
Results generated for hardware version 1.5.3.2.
| CPU Configuration | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|---|---|---|---|---|---|
rv32i |
980 | 409 | 1024 | 0 | 123 MHz |
rv32i + Zicsr |
1835 | 856 | 1024 | 0 | 124 MHz |
rv32imac + Zicsr |
2685 | 1156 | 1024 | 0 | 124 MHz |
rv32imac + Zicsr + u + Zifencei + Zfinx |
4004 | 1812 | 1024 | 7 | 121 MHz |
The NEORV32 CPU is based on a two-stages pipelined architecutre. Each stage uses a multi-cycle processing scheme.
Hence, each instruction requires several clock cycles to execute (2 cycles for ALU operations, and up to 40 cycles for divisions).
By default the CPU-internal shifter as well as the multiplier and divider of the M extension use a bit-serial approach
and require several cycles for completion. The average CPI (cycles per instruction) depends on the instruction mix of a
specific applications and also on the available CPU extensions.
The following table shows the performance results(relative CoreMark score and average cycles per instruction) for successfully running 2000 iterations of the CoreMark CPU benchmark, which reflects a pretty good "real-life" work load. The source files are available in sw/example/coremark.
**CoreMark Setup**
Hardware: 32kB IMEM, 8kB DMEM, no caches, 100MHz clock
CoreMark: 2000 iterations, MEM_METHOD is MEM_STACK
Compiler: RISCV32-GCC 10.1.0 (rv32i toolchain)
Compiler flags: default, see makefile; optimization -O3
Results generated for hardware version 1.4.9.8.
CPU (including Zicsr extension) |
Executable Size | CoreMark Score | CoreMarks/MHz | Total Clock Cycles | Executed Instructions | Average CPI |
|---|---|---|---|---|---|---|
rv32i |
28 756 bytes | 36.36 | 0.3636 | 5595750503 | 1466028607 | 3.82 |
rv32imc |
22 008 bytes | 68.97 | 0.6897 | 2981786734 | 611814918 | 4.87 |
rv32imc + FAST_MUL_EN + FAST_SHIFT_EN |
22 008 bytes | 90.91 | 0.9091 | 2265135174 | 611814948 | 3.70 |
ℹ️ The FAST_MUL_EN configuration uses DSPs for the multiplier of the M extension.
The FAST_SHIFT_EN configuration uses a barrel shifter for CPU shift operations.
📚 In-depth detailed information regarding the software framework can be found in the online documentation - "Software Framework".
- core libraries for high-level usage of the provided functions and peripherals
- application compilation based on GNU makefiles
- gcc-based toolchain (pre-compiled toolchains available)
- bootloader with UART interface console
- runtime environment for handling traps
- several example programs to get started including CoreMark, FreeRTOS and Conway's Game of Life
doxygen-based documentation, available on GitHub pages- supports implementation using open source tooling (GHDL, Yosys and nextpnr; in the future Verilog-to-Routing); both, software and hardware can be developed and debugged with open source tooling
- continuous Integration is available for:
- allowing users to see the expected execution/output of the tools
- ensuring specification compliance
- catching regressions
- providing ready-to-use and up-to-date bitstreams and documentation
This overview provides some quick links to the most important sections of the online Data Sheet and the online User Guide.
-
Rationale - NEORV32: why, how come, what for
-
NEORV32 Processor - the SoC
- Top Entity - Signals - how to connect to the processor
- Top Entity - Generics - configuration options
- Address Space - memory layout and boot configuration
- SoC Modules - available IO/peripheral modules and memories
- On-Chip Debugger - online & in-system debugging of the processor via JTAG
-
NEORV32 CPU - the RISC-V core
- RISC-V compatibility - what is compatible to the specs. and what is not
- ISA and Extensions - available RISC-V ISA extensions
- CSRs - control and status registers
- Traps - interrupts and exceptions
- Core Libraries - high-level functions for accessing the processor's peripherals
- Software Framework Documentation -
doxygen-based documentation
- Software Framework Documentation -
- Application Makefiles - turning your application into an executable
- Bootloader - the build-in NEORV32 bootloader
🚀 User Guides (see full User Guide)
- Toolchain Setup - install and setup RISC-V gcc
- General Hardware Setup - setup a new NEORV32 EDA project
- General Software Setup - configure the software framework
- Application Compilation - compile an application using
make - Upload via Bootloader - upload and execute executables
- Debugging via the On-Chip Debugger - step through code online and in-system
A big shoutout to all contributors, who helped improving this project! ❤️
RISC-V - Instruction Sets Want To Be Free!
Continous integration provided by 
GitHub Actions and powered by GHDL.
Made with ☕ in Hannover, Germany 🇪🇺