Pinned Repositories
almond
A Scala kernel for Jupyter
AXI_code
Bedrock
LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
biriscv
32-bit Superscalar RISC-V CPU
ChatGPT-Paper-Reader
This repo offers a simple interface that helps you to read&summerize research papers in pdf format. You can ask some questions after reading. This interface is developed based on openai API and using GPT-3.5-turbo model.
core_mmc
MMC (and derivative standards) host controller
dma_ip_drivers
Xilinx QDMA IP Drivers
FPGA
gpt4-pdf-chatbot-langchain
GPT4 & LangChain Chatbot for large PDF docs
ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
sujianleo's Repositories
sujianleo/Xilinx-FPGA-PCIe-XDMA-Tutorial
Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核
sujianleo/ZYNQ-NVDLA
NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
sujianleo/almond
A Scala kernel for Jupyter
sujianleo/AXI_code
sujianleo/Bedrock
LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
sujianleo/biriscv
32-bit Superscalar RISC-V CPU
sujianleo/ChatGPT-Paper-Reader
This repo offers a simple interface that helps you to read&summerize research papers in pdf format. You can ask some questions after reading. This interface is developed based on openai API and using GPT-3.5-turbo model.
sujianleo/core_mmc
MMC (and derivative standards) host controller
sujianleo/dma_ip_drivers
Xilinx QDMA IP Drivers
sujianleo/FPGA
sujianleo/gpt4-pdf-chatbot-langchain
GPT4 & LangChain Chatbot for large PDF docs
sujianleo/hdl
HDL libraries and projects
sujianleo/iob-mem
Verilog behavioral description of various memories
sujianleo/no-OS
Software drivers in C for systems without an operating system
sujianleo/pp4fpgas-cn
中文版 Parallel Programming for FPGAs
sujianleo/Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
sujianleo/SpinalHDL
Scala based HDL
sujianleo/SpinalTemplateSbt
A basic SpinalHDL project
sujianleo/UART-RS232
RS232 Receiver/Transmitter Verilog for FPGA
sujianleo/verilog-can
Verilog CAN controller that is compatible to the SJA 1000.
sujianleo/riscv64-linux
sujianleo/srio_test
Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
sujianleo/tvm
Open deep learning compiler stack for cpu, gpu and specialized accelerators