sumanth-kalluri

128-Bit-AES-Encryption-and-Decryption-in-Verilog

This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.

cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Drowsiness-detection-and-sleep-prevention-system-for-drivers

This was a project that was built in Hackfest 2017 of IIT-ISM Dhanbad.

git_sample_repo

IRis

An IR Based Audience Response System

low-latency-ethernet

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

numpy-100

100 numpy exercises (100% complete)

sumanth-kalluri/cnn_hardware_acclerator_for_fpga

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

sumanth-kalluri/128-Bit-AES-Encryption-and-Decryption-in-Verilog

This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.

sumanth-kalluri/Driver_Example_CCS

Drivers y Ejemplos para CCS sobre PIC

sumanth-kalluri/Drowsiness-detection-and-sleep-prevention-system-for-drivers

This was a project that was built in Hackfest 2017 of IIT-ISM Dhanbad.

sumanth-kalluri/git_sample_repo

sumanth-kalluri/IRis

An IR Based Audience Response System

sumanth-kalluri/low-latency-ethernet

RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.

sumanth-kalluri/numpy-100

100 numpy exercises (100% complete)