Pinned Repositories
Analog-Signal-Interfacing-and-Filtering-using-FPGA-in-VHDL
Read the digitized values of an analog signal connected to ADC input on Spartan 3E board, do some digital filtering on these samples and output through the DAC on board, display both the input and output on a CRO. You can also use Pmod ADC with BASYS3 Board.
Band-Stacking-Landsat-Image
Stacking the Bands of Landsat Multi-Spectral Image to create a single TIF file
Fire-Detection-from-FLAME-Dataset
Deep Learning model implementation for Fire detection both classification and segmentation from the FLAME dataset.
HDL_Basic_Circuits
This is the repository of some of the digital system circuits coded in HDL both in VHDL and Verilog starting from basic level to little advance level.
Image-Conversions
This is the function to interpolate any image using different Interpolation technique
Linux-Tutorials
Things to be done in linux and problems faced by me
Python-Basic-Programs
Basic Python Problems with lists, tuples etc.
Rectifier-with-Capacitor-Filter
Design of a Bridge Rectifier with Capacitor Filter for AC to DC Conversion
Spice-Model-Collections
All the spice model collected from different sources at a single space
TCP-IP-Basic-Tasks
sunnyiisc's Repositories
sunnyiisc/Fire-Detection-from-FLAME-Dataset
Deep Learning model implementation for Fire detection both classification and segmentation from the FLAME dataset.
sunnyiisc/Spice-Model-Collections
All the spice model collected from different sources at a single space
sunnyiisc/HDL_Basic_Circuits
This is the repository of some of the digital system circuits coded in HDL both in VHDL and Verilog starting from basic level to little advance level.
sunnyiisc/Image-Conversions
This is the function to interpolate any image using different Interpolation technique
sunnyiisc/Analog-Signal-Interfacing-and-Filtering-using-FPGA-in-VHDL
Read the digitized values of an analog signal connected to ADC input on Spartan 3E board, do some digital filtering on these samples and output through the DAC on board, display both the input and output on a CRO. You can also use Pmod ADC with BASYS3 Board.
sunnyiisc/Band-Stacking-Landsat-Image
Stacking the Bands of Landsat Multi-Spectral Image to create a single TIF file
sunnyiisc/Basic-Projects-in-Python
Some Programs for Practice in Python
sunnyiisc/CPP-Basic-Programs
Some basic Programs in C++
sunnyiisc/Cropping-Raster-based-on-ROI
Cropping a Raster based on the Region of Interest (ROI)
sunnyiisc/File-Folder-Selection-GUI-in-Python
This is a simple GUI that can be used in any python program for selecting files or folders using GUI
sunnyiisc/Linux-Tutorials
Things to be done in linux and problems faced by me
sunnyiisc/Python-Basic-Programs
Basic Python Problems with lists, tuples etc.
sunnyiisc/Rectifier-with-Capacitor-Filter
Design of a Bridge Rectifier with Capacitor Filter for AC to DC Conversion
sunnyiisc/TCP-IP-Basic-Tasks
sunnyiisc/EnMap-Data-PreProcessing
sunnyiisc/Ground-Reflectance-to-TOA-Converter-using-6S
Bottom of Atmosphere Reflectance to Top of Atmosphere Simulation
sunnyiisc/HelloWorld
testing
sunnyiisc/Linear-IC-based-Regulator
Linear IC based Voltage Regulator (LM317) for DC to DC conversion following the Bridge Rectifier
sunnyiisc/markdown-content
Markdown content for the www.aerobatic.io website
sunnyiisc/NC-to-TIFF-stack
Program to convert a raster file in NetCdf format to TIFF format with all the bands stacked
sunnyiisc/Resourcesat-PreProcessor
Converting the HDF Product to Georeferenced TIFF.
sunnyiisc/Signed-8-bit-Radix-4-Booth-Recoded-Array-Multiplier-in-VHDL
Design and Implement a signed 8-bit Radix-4 Booth Recoded Array Multiplier (All partial products are generated and added concurrently) using VHDL code. Do the structural coding using components for booth recoding. Partial products can be added using in-built operator + that would use Carry Propagate Adder resource within FPGA.
sunnyiisc/Single-Phase-Inverter-12VDC-to-240VAC-50Hz
Design of a Inverter Converting 12VDC to 240V single phase AC delivering 5kVA load
sunnyiisc/sunnyiisc
Config files for my GitHub profile.
sunnyiisc/Three-Phase-Inverter-12VDC-to-440VAC-3ph-50Hz
Design of a Inverter Converting 12VDC to 440V three phase AC delivering 5kVA load
sunnyiisc/Verilog_Practice_Programs
This contains the programs that I have used while learning verilog.
sunnyiisc/YouTube_Downloader-Customized
This is a simple python program to download the contents of youtube for offline access.