/mips-cpu

A MIPS CPU implemented in Verilog

Primary LanguageVerilogMIT LicenseMIT

mips-cpu

A MIPS CPU implemented in Verilog

This is a course project of ACM Honored Class @ SJTU (wiki)

Features

  • 32-bit MIPS instruction
  • 5-stage pipeline
  • set-associative cache
  • runnable on FPGA (tested on XC7A35T)
  • memory simulated by C++ program (use UART)