- Tools installed
- Magic
- Xschem
- Ngspice
- Netgen
- ALIGN
- Pre-layout simulation for an inverter
- Inverter schematic in Xschem
- Making symbol
- Test and simulate the inverter
- Post-layout simulation for an inverter
- Layout implementation
- Run LVS with using netgen
- Post-layout simulation
- Generating layout with using Align
- Post-layout simulation for Inverter by using Align
- Pre-layout simulation of FN
- Schematic implementation
- Test and simulation
- Calculation of the delay
- Post-layout simulation of FN
- Layout implementation with Align
- Extracting parasitic capicitances using magic
- Post-layout simulation
- comparison between pre-layout and post-layout
- OpenFASoC installation
- Openroad installation
- Yosys installation
- Klayout installation
- OpenFASoC installation
- Running a sample using OpenFASoC
- Circuit structure
- Verilog generation
- Synthesis
- Basics of ring oscillator
- Pre-layout simulation of a ring oscillator
- Schematic implementation
- Test and simulation
- calculation of the period
- Post-layout simulation of a ring oscillator
- Layout implementation with Align
- Extracting parasitic capicitances using magic
- Post-layout simulation
- comparison between pre-layout and post-layout
- Basics of Analog to Digital Converter
- 1-Bit ADC
- Pre-Layout Simulation of a 1-Bit ADC
- Schematic implementation
- calculation of the period
- Post-Layout Simulation of a 1-Bit ADC
- Layout implementation with Align
- Extracting parasitic capicitances using magic
- Post-layout simulation
- Comparison Between Post-Layout and Pre-Layout Results of ADC
- Pre-Layout simulation of combination of RO and ADC(RO_ADC)
- Post-Layout simulation of RO_ADC
- Comparison of Pre and Post-Layout results of RO_ADC
- Top Module of Verilog Code for RO and ADC
- Layout implementation for Ring Oscillator and ADC using OpenFASoC
- Reduce the area of the Macro in OpenFASoC
- Connect the VDD and VSS to the Macro