Pinned Repositories
fpga-sdk-prj
FPGA-based SDK projects for SCRx cores
libjaylink
Just a working copy of http://repo.or.cz/r/libjaylink.git
openocd
OpenOCD Syntacore targets
riscv-binutils-gdb
RISC-V port of GDB
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
rvv-simulator
RISC-V vector extension ISA simulation
sc-bl
Syntacore first stage bootloader
scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
scr1-sdk
open-source SDKs for the SCR1 core
snippy
Syntacore's Repositories
syntacore/scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
syntacore/scr1-sdk
open-source SDKs for the SCR1 core
syntacore/snippy
syntacore/fpga-sdk-prj
FPGA-based SDK projects for SCRx cores
syntacore/libjaylink
Just a working copy of http://repo.or.cz/r/libjaylink.git
syntacore/rvv-simulator
RISC-V vector extension ISA simulation
syntacore/sc-bl
Syntacore first stage bootloader
syntacore/openocd
OpenOCD Syntacore targets
syntacore/riscv-binutils-gdb
RISC-V port of GDB
syntacore/riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
syntacore/linux
syntacore/boringssl
Mirror of BoringSSL
syntacore/opensbi
syntacore/riscv-clang
syntacore/riscv-dbg-proposal
RISC-V Debug Specification update proposal
syntacore/riscv-isa-manual
RISC-V Instruction Set Manual
syntacore/riscv-v-spec
Working draft of the proposed RISC-V V vector extension
syntacore/syntaj17
syntacore/zephyr
Primary GIT Repository for the Zephyr Project
syntacore/berkeley-softfloat-3
SoftFloat release 3
syntacore/cs152-sp18-lab4
syntacore/dining-philosophers
Simple c++11 demo of "Dining philosophers problem"
syntacore/jimtcl
Official mirror of Jim Tcl, an open-source, small footprint implementation of Tcl
syntacore/openssh-portable
Portable OpenSSH
syntacore/openssl
TLS/SSL and crypto library
syntacore/qemu
syntacore/riscv-compliance
syntacore/riscv-gcc
syntacore/syntaj21
https://openjdk.org/projects/jdk-updates
syntacore/tiny-dnn
header only, dependency-free deep learning framework in C++11