This repo contains all assignments and the course project. The assignments and projects involved simualting different basic circuital elements, logic gates and other combinational circuit layouts
Primary Languages Used
- NGSPICE
- MAGIC
- Verilog
Design a 4-bit carry look ahead (CLA) adder as shown in Fig. 1(i). Different modules of the CLA-adder are shown in Fig. 1(ii). Each output sum bit needs to drive an inverter of size Wp/Wn = 20λ/10λ, where λ = 0.09μm. As shown in Fig. 1(iii), consider that input bits are available before the rising edge of the clock and the output should be computed and present at the next rising edge of the clock. You can choose any logic style (static, dynamic, mix) to implement the circuit.
