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Verilog Language and Application v27.0

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📦 Cloning course files (Restricted)

git submodule update --init

Xcelium


📫 Contributing to this repository

Contributions are what make the open source community an amazing place to learn, inspire and create. Any contributions you make are very welcome!

If you want to help by suggesting text and spelling corrections or some code tweaks, you can open a pull request and I'll love it!!! 😍

If you have a quick contribution that doesn't involve code, content or you want to report a problem without having to propose changes click here to create an issue.

If not, follow these steps

  1. Fork this repository.
  2. Create a branch: git checkout -b newResource.
  3. Add your edits for the next commit: git add .
  4. Make your changes and confirm them: git commit -m 'Message from your contribution'.
  5. Specify a new upstream remote repository that will be synchronized with the fork: git remote add upstream git@github.com:<USER_NAME>/<REPOSITOR_NAME>.git
  6. Send to the original branch: git push --set-upstream origin newResource
  7. Create the pull request using the link that appears in the terminal.

🤝 Contributors

We would like to thank the following people who contributed to this project:

Foto do Maurício Taffarel no GitHub
Maurício Taffarel

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