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VectorCGRA (vectorizable Coarse-Grained Reconfigurable Accelerator) generator is a parameterizable CGRA generator to generate synthesizable Verilog for different CGRAs based on user-specified configurations (e.g., CGRA size, type of the computing units in each tile, number of lanes for vectorization, communication connection, etc.).
VectorCGRA should work well on Python 3.7/3.8/3.9/3.10 with the following additional prerequisites:
- graphviz, verilator
- git, Python headers, and libffi
- virtualenv
- PyMTL3
The steps for installing these prerequisites and VectorCGRA on a fresh Ubuntu distribution are shown below. They have been tested with Ubuntu Trusty 14.04 ~ 20.04.
% sudo apt-get install python3.7
% sudo apt-get install -y graphviz
Verilator is an open-source toolchain for compiling Verilog RTL models into C++ simulators. VectorCGRA uses Verilator for Verilog import.
$ sudo apt-get install git make autoconf g++ libfl-dev bison
$ mkdir -p ${HOME}/src
$ cd ${HOME}/src
$ wget http://www.veripool.org/ftp/verilator-4.036.tgz
$ tar -xzvf verilator-4.036.tgz
$ cd verilator-4.036
$ ./configure
$ make
$ sudo make install
We need to install the Python headers and libffi in order to be able to install the cffi Python package. cffi provides an elegant way to call C functions from Python, and PyMTL uses cffi to call C code generated by Verilator. We will use git to grab the PyMTL source. The following commands will install the appropriate packages:
% sudo apt-get install git python-dev libffi-dev
While not strictly necessary, we strongly recommend using virtualenv to install PyMTL3 and the Python packages that PyMTL3 depends on. virtualenv enables creating isolated Python environments. The following commands will create and activate the virtual environment:
% python3 -m venv ${HOME}/venv
% source ${HOME}/venv/bin/activate
% pip install py==1.11.0
% pip install -U git+https://github.com/tancheng/pymtl3.1@yo-struct-list-fix
% pip install --upgrade pip setuptools twine
% pip install hypothesis
% pip list
Take a look at the workflow if you encounter any problem to run the test in this repo.
We can now use git to clone the VectorCGRA repo.
% mkdir -p ${HOME}/cgra
% cd ${HOME}/cgra
% git clone https://github.com/tancheng/VectorCGRA.git
% git submodule update --init
Note that if the submodule update fails, try change the url of [submodule "fu/pymtl3_hardfloat"] in the .git/config from git@github.com:pymtl/pymtl3-hardfloat.git to https://github.com/pymtl/pymtl3-hardfloat.git.
For CGRA translation, just type:
% pytest VectorCGRAKingMeshRTL_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd
--test-verilog is used to generate Verilog Code, --dump-vtb is used to generate the test bench, --dump-vcd is used to generate the Value Change Dump (VCD) file.
Note that the --dump-vtb need to be used with --test-verilog. --dump-vcd can be used without Verilog translation for different modules. For example, for Tile testing:
% pytest --tb=short -sv TileRTL_test.py --dump-vcd
When you're done testing/developing, you can deactivate the virtualenv::
% deactivate
@inproceedings{tan2023vecpac,
title={VecPAC: A Vectorizable and Precision-Aware CGRA},
author={Tan, Cheng and Patil, Deepak and Tumeo, Antonino and Weisz, Gabriel and Reinhardt, Steve and Zhang, Jeff},
booktitle={2023 IEEE/ACM International Conference On Computer Aided Design (ICCAD)},
year={2023},
organization={IEEE}
}