tarunky1

ALU_components

first verilog repository

crypto1

mips32

tarunky1/ALU_components

first verilog repository

tarunky1/crypto1

tarunky1/mips32

tarunky1/32bit_tree_adder

Tree adder for fast addition

tarunky1/barrel_shifter

tarunky1/cs50-pset1

tarunky1/integer_multiplier

tarunky1/vsdflow

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.