Pinned Repositories
gem5_data_proc
data preprocessing scripts for gem5 output
aura-core
"aura" my super-scalar O3 cpu core
FPGA_network
FPGA_verilog_easy_cpu
very easy cpu
FPGA_verilog_R8051
riscv-isa-sim
Spike, a RISC-V ISA Simulator
RITTER-RISCV-CORE
Five-stage pipeline riscv kernel designed with verilog
ritter-soc
a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
tastynoob.github.io
个人博客网站
TOYSOC
这是一个简单的状态机riscv cpu，使用verilog设计，用于启明星智能组暑期培训
tastynoob's Repositories
tastynoob/aura-core
"aura" my super-scalar O3 cpu core
tastynoob/ritter-soc
a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog
tastynoob/FPGA_verilog_easy_cpu
very easy cpu
tastynoob/TOYSOC
这是一个简单的状态机riscv cpu，使用verilog设计，用于启明星智能组暑期培训
tastynoob/RITTER-RISCV-CORE
Five-stage pipeline riscv kernel designed with verilog
tastynoob/balance_car
平衡小车
tastynoob/Fingerprint-gate
基于GD32VF的指纹留观闸机
tastynoob/NNQ
a BP network module frame using by c++
tastynoob/ONICPU-PSASM
ONICPU is a CPU mod for OxygenNotIncluded that allows you to build programmable code execution control units to implement complex automation functions.
tastynoob/SpiritLoong
tastynoob/QMXDOC
tastynoob/riscv-isa-sim
Spike, a RISC-V ISA Simulator
tastynoob/tastynoob.github.io
个人博客网站
tastynoob/aura-sim
"aura" my super-scala O3 cpu simulator
tastynoob/autotest
a auto test script used for gem5
tastynoob/BLANG
My programming language designed by python-lex-yacc(ply)
tastynoob/booth-muler
the booth mulre designed by verilog
tastynoob/eide
An embedded development environment for mcs51/stm8/avr/cortex-m/riscv on VsCode.
tastynoob/FAST-PSASM
simple customized asm and programming language , include a fast asm interpreter and lang compiler, used for embedded in games
tastynoob/gd32v_thread
A simple riscv multithreaded system
tastynoob/GPQ
a simple 3d Renderer
tastynoob/ICache
one Configurable ICache with pseudo LRU replacement strategy
tastynoob/nemu
NJU EMUlator, used for aura difftesting
tastynoob/riscv-decoder-generator
tastynoob/riscv-disasm
tastynoob/riscv-firmware
a template for EIDE riscv project
tastynoob/Software-Engineering-Test
tastynoob/teamManage
tastynoob/verilator
Verilator open-source SystemVerilog simulator and lint system
tastynoob/xs-GEM5-test