Single Cycle MIPS Processor implemented in VHDL Supported Instructions: + I-Type - ADDI + R-Type - ADD - SUB - AND - OR - SLT + Branch - BNE - BEQ + J-Type - J
Single Cycle MIPS Processor implemented in VHDL Supported Instructions: + I-Type - ADDI + R-Type - ADD - SUB - AND - OR - SLT + Branch - BNE - BEQ + J-Type - J