tcutee

tcutee's Stars

• LoveLonelyTime/LLTRISC-V

  LoveLonelyTime's RISC-V core basic version, RV32I, five pipeline stages.

  Language:C16

• LoveLonelyTime/Bergamot

  An exquisite superscalar RV32GC processor.

  Language:Scala13612

• zhongyuchen/mips-32bit

  Four versions of MIPS 32bit implemented in Verilog using Vivado, ready for Simulation and Nexys4 DDR Board

  Language:Verilog85

• RSPwFPGAs/virtio-fpga-bridge

  Virtio front-end and back-end bridge, implemented with FPGA.

  Language:SystemVerilog258

• AmirhosseinR/VeeRwolf

  VeeRwolf (a platform for the VeeR family of RISC-V cores) for Nexys Video Board: https://github.com/chipsalliance/VeeRwolf

  Language:Verilog22

• QQxiaoming/quard_star_tutorial

  This project aims to build an Embedded Linux System, in order to analyze the chip from the power-on execution of the first instruction to the entire system running, based on qemu simulator development board. 本项目旨在真正从0开始构建嵌入式linux系统，为了剖析芯片从上电开始执行第一条指令到整个系统运行，基于qemu定制模拟器开发板。

  Language:C24054

• alibaba/SiliconFastOS

  Language:C234