Due date: Sunday 10/2/2016 @11:59pm
Objective: Pipelining (Part III)
Adding a store instruction (it's harder than you might think)
Assignment:
You're given an inefficient multi-cycle implementation of our CPU. Your job
is it make it run as fast as you can by pipelining it.
Add a test case:
<your csid>.ok <your csid>.hex
My implementation is embarrassingly slow and you have plenty of room for
improvement.
- instruction set
encoding instruction description
0000iiiiiiiitttt mov i,t regs[t] = i; pc += 1;
0001aaaabbbbtttt add a,b,t regs[t] = regs[a] + regs[b]; pc += 1;
0010jjjjjjjjjjjj jmp j pc = j;
0011000000000000 halt <stop fetching instructions>
0100iiiiiiiitttt ld i,t regs[t] = mem[i]; pc += 1;
0101aaaabbbbtttt ldr a,b,t regs[t] = mem[regs[a]+regs[b]]; pc += 1;
0110aaaabbbbtttt jeq a,b,t if (regs[a] == regs[b]) pc += d
else pc += 1;
0111aaaassssssss st s,a mem[s] = regs[a]; pc += 1;
Files you can change
~~~~~~~~~~~~~~~~~~~~
cpu.v contains the implementation. You are required to use the provided
memory (mem.v), register file (regs.v), and clock (clock.v)
Files to leave alone
~~~~~~~~~~~~~~~~~~~~
Makefile, clock.v, mem.v, regs.v, counter.v, test.ok, mem.hex
To compile
~~~~~~~~~~
make
To run
~~~~~~
make run
Will also produce cpu.vcd which can be viewed in gtkwave
To test
~~~~~~~
make test