This project is a five stage pipelined MIPS processor with mitigation strategies to solve data and control hazards. It has been implemented and simulated on Vivado HLS 2020.2 and coded entirely in Verilog.
A MIPS pipelined processor faces several data hazards and control hazards. A detailed report of the strategies used to mitigate each of the data and control hazards is also added.
Download the entire mips folder and double click on mips.xpr to open the project in your Vivado Software.