tejashah94/AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
VerilogApache-2.0
No issues in this repository yet.
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
VerilogApache-2.0
No issues in this repository yet.