thegabriele97/DLX-RISC-CPU

Issues

• [DOC] Conclusion

  #83 opened 4 years ago by MatteoBattilana
  0

• [DOC] Decode - Instruction Decode

  #80 opened 4 years ago by thegabriele97
  1

• [DOC] Decode Stage

  #54 opened 4 years ago by giovannipollo
  1

• [DOC] Register file - diagram and link blocks to the abstract

  #58 opened 4 years ago by MatteoBattilana
  2

• [DOC] Post Synthesis Simulation

  #78 opened 4 years ago by MatteoBattilana
  2

• [DOC] Feature

  #82 opened 4 years ago by MatteoBattilana
  0

• [DOC] Add Control Words to Control Unit

  #81 opened 4 years ago by thegabriele97
  0

• [DOC] Place and Route

  #75 opened 4 years ago by MatteoBattilana
  0

• [DOC] Overview - Pipeline stages

  #73 opened 4 years ago by thegabriele97
  0

• [DOC] Synthesis

  #79 opened 4 years ago by MatteoBattilana
  0

• [DOC] Simulation

  #76 opened 4 years ago by MatteoBattilana
  0

• [DOC] Test Benches

  #77 opened 4 years ago by MatteoBattilana
  0

• [DOC] Instruction Register

  #69 opened 4 years ago by MatteoBattilana
  0

• [DOC] Load-Store Unit

  #74 opened 4 years ago by MatteoBattilana
  0

• [DOC] Instruction Set

  #61 opened 4 years ago by thegabriele97
  0

• [DOC] Write Back Stage

  #63 opened 4 years ago by giovannipollo
  0

• [DOC] Write Back Stage

  #72 opened 4 years ago by MatteoBattilana
  0

• [DOC] FSM diagram CU for WRF

  #70 opened 4 years ago by MatteoBattilana
  3

• [DOC] Check completeness of Fetch Stage

  #71 opened 4 years ago by MatteoBattilana
  1

• Simplify P4 Adder inside decoder

  #29 opened 4 years ago by thegabriele97
  2

• Replace adder with P4 adder inside the multiplier

  #48 opened 4 years ago by thegabriele97
  4

• [DOC] Execute Stage

  #68 opened 4 years ago by MatteoBattilana
  0

• [DOC] Set-Like Operations unit

  #66 opened 4 years ago by MatteoBattilana
  0

• [DOC] Comparator

  #67 opened 4 years ago by MatteoBattilana
  0

• [DOC] ALU: Arithmetic Logic Unit

  #65 opened 4 years ago by MatteoBattilana
  0

• [DOC] Revise multiplier

  #64 opened 4 years ago by MatteoBattilana
  0

• [DOC] Adder

  #62 opened 4 years ago by MatteoBattilana
  4

• [DOC] Multiplier

  #59 opened 4 years ago by MatteoBattilana
  0

• [DOC] HW architecture - Control Unit

  #60 opened 4 years ago by thegabriele97
  0

• [DOC] DLX - Memory Interface

  #55 opened 4 years ago by thegabriele97
  0

• Move all the cleverness of the memory inside the core

  #44 opened 4 years ago by thegabriele97
  2

• [DOC] Register file - only presentation abstract, no diagram

  #57 opened 4 years ago by MatteoBattilana
  0

• [DOC] Execute Stage - ALU - Shifting

  #52 opened 4 years ago by MatteoBattilana
  0

• [DOC] Hardware Architecture - Overview

  #50 opened 4 years ago by thegabriele97
  0

• First working implementation of the DLX

  #23 opened 4 years ago by thegabriele97
  1

• [DOC] Introduction

  #56 opened 4 years ago by giovannipollo
  0

• [DOC] Execute Stage - ALU - Logic Operands

  #51 opened 4 years ago by MatteoBattilana
  2

• Replace control words in the CU with records (C-like structs)

  #46 opened 4 years ago by thegabriele97
  3

• Remove all the 'X' in the control words

  #43 opened 4 years ago by thegabriele97
  0

• Pipeline Stall when the signal DRAM_READY is not high

  #42 opened 4 years ago by thegabriele97
  1

• Check correctness of Hazard Control

  #25 opened 4 years ago by thegabriele97
  0

• PRO DLX Instruction Set Implementation

  #35 opened 4 years ago by thegabriele97
  2

• Simpler indexing writing in CU_HW.vhd

  #32 opened 4 years ago by thegabriele97
  2

• BASE DLX Instruction Set Implementation

  #37 opened 4 years ago by thegabriele97
  0

• LD/STR address should be able to address single bytes

  #38 opened 4 years ago by thegabriele97
  4

• Do constants for the instruction OP_CODE inside globals

  #34 opened 4 years ago by giovannipollo
  1

• MULT integer implementation

  #33 opened 4 years ago by thegabriele97
  2

• Excel spreadsheet for the control unit

  #30 opened 4 years ago by giovannipollo
  1

• Draw the Control Word and ALU Opcode

  #28 opened 4 years ago by giovannipollo
  0

• Fix Data Path signal

  #27 opened 4 years ago by giovannipollo
  0