Experimental-Convolution-Engine
FPGA implementation - VHDL code
Use half-precision floating-point format IEEE 754-2008
Kernel 3x3
tirfil/Experimental-Convolution-Engine
Experimental Convolution Engine FPGA implementation - VHDL code Use half-precision floating-point format IEEE 754-2008 Kernel 3x3
VHDLGPL-3.0